/*\r
- FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
the terms of the GNU General Public License (version 2) as published by the\r
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
\r
#include <FreeRTOSConfig.h>\r
\r
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
-defined. The value zero should also ensure backward compatibility.\r
-FreeRTOS.org versions prior to V4.3.0 did not include this definition. */\r
-#ifndef configKERNEL_INTERRUPT_PRIORITY\r
- #define configKERNEL_INTERRUPT_PRIORITY 0\r
-#endif\r
-\r
- \r
RSEG CODE:CODE(2)\r
thumb\r
\r
PUBLIC xPortPendSVHandler\r
PUBLIC vPortSVCHandler\r
PUBLIC vPortStartFirstTask\r
-\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
\r
/*-----------------------------------------------------------*/\r
\r
vSetMSP\r
msr msp, r0\r
bx lr\r
- \r
+\r
/*-----------------------------------------------------------*/\r
\r
xPortPendSVHandler:\r
- mrs r0, psp \r
- \r
+ mrs r0, psp\r
+\r
ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */\r
- ldr r2, [r3] \r
- \r
+ ldr r2, [r3]\r
+\r
subs r0, r0, #32 /* Make space for the remaining low registers. */\r
str r0, [r2] /* Save the new top of stack. */\r
stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */\r
mov r4, r8 /* Store the high registers. */\r
- mov r5, r9 \r
- mov r6, r10 \r
- mov r7, r11 \r
- stmia r0!, {r4-r7} \r
- \r
- push {r3, r14} \r
- cpsid i \r
- bl vTaskSwitchContext \r
- cpsie i \r
+ mov r5, r9\r
+ mov r6, r10\r
+ mov r7, r11\r
+ stmia r0!, {r4-r7}\r
+\r
+ push {r3, r14}\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */\r
- \r
- ldr r1, [r2] \r
+\r
+ ldr r1, [r2]\r
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */\r
adds r0, r0, #16 /* Move to the high registers. */\r
ldmia r0!, {r4-r7} /* Pop the high registers. */\r
- mov r8, r4 \r
- mov r9, r5 \r
- mov r10, r6 \r
- mov r11, r7 \r
- \r
+ mov r8, r4\r
+ mov r9, r5\r
+ mov r10, r6\r
+ mov r11, r7\r
+\r
msr psp, r0 /* Remember the new top of stack for the task. */\r
- \r
+\r
subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */\r
ldmia r0!, {r4-r7} /* Pop low registers. */\r
- \r
- bx r3 \r
+\r
+ bx r3\r
\r
/*-----------------------------------------------------------*/\r
\r
vPortSVCHandler;\r
- ldr r3, =pxCurrentTCB /* Restore the context. */\r
- ldr r1, [r3] /* Get the pxCurrentTCB address. */\r
- ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */\r
- adds r0, r0, #16 /* Move to the high registers. */\r
- ldmia r0!, {r4-r7} /* Pop the high registers. */\r
- mov r8, r4 \r
- mov r9, r5 \r
- mov r10, r6 \r
- mov r11, r7 \r
- \r
- msr psp, r0 /* Remember the new top of stack for the task. */\r
- \r
- subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */\r
- ldmia r0!, {r4-r7} /* Pop low registers. */\r
- mov r1, r14 /* OR R14 with 0x0d. */\r
- movs r0, #0x0d \r
- orrs r1, r0 \r
- bx r1 \r
+ /* This function is no longer used, but retained for backward\r
+ compatibility. */\r
+ bx lr\r
\r
/*-----------------------------------------------------------*/\r
\r
vPortStartFirstTask\r
- movs r0, #0x00 /* Locate the top of stack. */\r
- ldr r0, [r0] \r
- msr msp, r0 /* Set the msp back to the start of the stack. */\r
- cpsie i /* Globally enable interrupts. */\r
- svc 0 /* System call to start first task. */\r
- nop \r
- \r
+ /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector\r
+ table offset register that can be used to locate the initial stack value.\r
+ Not all M0 parts have the application vector table at address 0. */\r
+\r
+ ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */\r
+ ldr r1, [r3]\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ movs r0, #2 /* Switch to the psp stack. */\r
+ msr CONTROL, r0\r
+ pop {r0-r5} /* Pop the registers that are saved automatically. */\r
+ mov lr, r5 /* lr is now in r5. */\r
+ cpsie i /* The first task has its context and interrupts can be enabled. */\r
+ pop {pc} /* Finally, pop the PC to jump to the user defined task code. */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR\r
+ msr PRIMASK, r0\r
+ bx lr\r
+\r
END\r
-
\ No newline at end of file