/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r