calculations. */\r
#define portMISSED_COUNTS_FACTOR ( 45UL )\r
\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )\r
\r
/* Each task maintains its own interrupt status in the critical nesting\r
variable. */\r
\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\r
pxTopOfStack--;\r
*pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
__disable_interrupt();\r
+ __DSB();\r
+ __ISB();\r
+\r
\r
/* If a context switch is pending or a task is waiting for the scheduler\r
to be unsuspended then abandon the low power entry. */\r