Changes to core code and port layer:

[freertos] / FreeRTOS / Source / portable / MikroC / ARM_CM4F / port.c

diff --git a/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c b/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
index bb6993348194d9ef9a8ab304a9282a28db69a83b..451518799613e8f521eab78778acd9023436d4da 100644 (file)
--- a/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
+++ b/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
@@ -153,6 +153,7 @@ is defined. */
 #define basepri        17\r
 #define msp            8\r
 #define ipsr   5\r
+#define control        20\r
 \r
 /* From port.c. */\r
 extern void *pxCurrentTCB;\r
@@ -287,7 +288,7 @@ void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
                        ldm r0!, (r4-r11, r14)/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
                        msr psp, r0                             /* Restore the task stack pointer. */\r
                        isb\r
-                                  mov r0, #0\r
+                       mov r0, #0\r
                        msr basepri, r0\r
                        bx r14\r
        };\r
@@ -299,8 +300,14 @@ static void prvPortStartFirstTask( void )
        __asm {\r
                                ldr r0, =0xE000ED08      /* Use the NVIC offset register to locate the stack. */\r
                                ldr r0, [r0]\r
-                                               ldr r0, [r0]\r
+                               ldr r0, [r0]\r
                                msr msp, r0                      /* Set the msp back to the start of the stack. */\r
+                               /* Clear the bit that indicates the FPU is in use in case the FPU was used\r
+                               before the scheduler was started - which would otherwise result in the\r
+                               unnecessary leaving of space in the SVC stack for lazy saving of FPU\r
+                               registers. */\r
+                               mov r0, #0\r
+                               msr control, r0\r
                                cpsie i                          /* Globally enable interrupts. */\r
                                cpsie f\r
                                dsb\r
@@ -357,6 +364,24 @@ BaseType_t xPortStartScheduler( void )
                        ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
                }\r
 \r
+               #ifdef __NVIC_PRIO_BITS\r
+               {\r
+                       /* Check the CMSIS configuration that defines the number of\r
+                       priority bits matches the number of priority bits actually queried\r
+                       from the hardware. */\r
+                       configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+               }\r
+               #endif\r
+\r
+               #ifdef configPRIO_BITS\r
+               {\r
+                       /* Check the FreeRTOS configuration that defines the number of\r
+                       priority bits matches the number of priority bits actually queried\r
+                       from the hardware. */\r
+                       configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+               }\r
+               #endif\r
+\r
                /* Shift the priority group value back to its position within the AIRCR\r
                register. */\r
                ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r