/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
\r
***************************************************************************\r
>>! NOTE: The modification to the GPL is included to allow you to !<<\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
+\r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE ( 15 )\r
+\r
/*-----------------------------------------------------------*/\r
\r
/* Scheduler utilities. */\r
-extern void vPortYield( void );\r
+#define portYIELD() \\r
+{ \\r
+ /* Set a PendSV to request a context switch. */ \\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\r
+ \\r
+ /* Barriers are normally not required but do ensure the code is completely \\r
+ within the specified behaviour for the architecture. */ \\r
+ __dsb( portSY_FULL_READ_WRITE ); \\r
+ __isb( portSY_FULL_READ_WRITE ); \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
-#define portYIELD() vPortYield()\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\r
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Critical section management. */\r
-extern uint32_t ulPortSetInterruptMask( void );\r
-extern void vPortClearInterruptMask( uint32_t ulNewMask );\r
extern void vPortEnterCritical( void );\r
extern void vPortExitCritical( void );\r
\r
-#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()\r
-#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )\r
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()\r
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)\r
+\r
/*-----------------------------------------------------------*/\r
\r
/* Tickless idle/low power functionality. */\r
\r
/*-----------------------------------------------------------*/\r
\r
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )\r
\r
#endif /* taskRECORD_READY_PRIORITY */\r
/*-----------------------------------------------------------*/\r
/* portNOP() is not required by this port. */\r
#define portNOP()\r
\r
+#define portINLINE __inline\r
+\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE __forceinline\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\r
+{\r
+ __asm\r
+ {\r
+ /* Barrier instructions are not used as this function is only used to\r
+ lower the BASEPRI value. */\r
+ msr basepri, ulBASEPRI\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to the max syscall priority to effect a critical\r
+ section. */\r
+ msr basepri, ulNewBASEPRI\r
+ dsb\r
+ isb\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )\r
+{\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to 0 so no interrupts are masked. This function is only\r
+ used to lower the mask in an interrupt, so memory barriers are not \r
+ used. */\r
+ msr basepri, #0\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to the max syscall priority to effect a critical\r
+ section. */\r
+ mrs ulReturn, basepri\r
+ msr basepri, ulNewBASEPRI\r
+ dsb\r
+ isb\r
+ }\r
+\r
+ return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ __asm\r
+ {\r
+ mrs ulCurrentInterrupt, ipsr\r
+ }\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r