/*\r
- FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
This file is part of the FreeRTOS distribution.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
link: http://www.freertos.org/a00114.html\r
\r
- 1 tab == 4 spaces!\r
-\r
***************************************************************************\r
* *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
* *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
* *\r
***************************************************************************\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
\r
http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
engineered and independently SIL3 certified version for use in safety and\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\r
+r0p1 port. */\r
+#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\r
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )\r
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )\r
+\r
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
#define portPRIGROUP_SHIFT ( 8UL )\r
\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
+\r
/* Constants required to manipulate the VFP. */\r
#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
#define portINITIAL_XPSR ( 0x01000000 )\r
#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
\r
-/* Constants used with memory barrier intrinsics. */\r
-#define portSY_FULL_READ_WRITE ( 15 )\r
-\r
/* The systick is a 24-bit counter. */\r
#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
\r
msr msp, r0\r
/* Globally enable interrupts. */\r
cpsie i\r
+ cpsie f\r
dsb\r
isb\r
/* Call SVC to start the first task. */\r
svc 0\r
nop\r
+ nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
*/\r
BaseType_t xPortStartScheduler( void )\r
{\r
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+ /* This port can be used on all revisions of the Cortex-M7 core other than\r
+ the r0p1 parts. r0p1 parts should use the port from the\r
+ /source/portable/GCC/ARM_CM7/r0p1 directory. */\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\r
+\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
/* Read the value back to see how many bits stuck. */\r
ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
+ /* The kernel interrupt priority should be set to the lowest\r
+ priority. */\r
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\r
+\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortYield( void )\r
-{\r
- /* Set a PendSV to request a context switch. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
-\r
- /* Barriers are normally not required but do ensure the code is completely\r
- within the specified behaviour for the architecture. */\r
- __dsb( portSY_FULL_READ_WRITE );\r
- __isb( portSY_FULL_READ_WRITE );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void vPortEnterCritical( void )\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
- __dsb( portSY_FULL_READ_WRITE );\r
- __isb( portSY_FULL_READ_WRITE );\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
stmdb sp!, {r3}\r
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
msr basepri, r0\r
+ dsb\r
+ isb\r
bl vTaskSwitchContext\r
mov r0, #0\r
msr basepri, r0\r
#endif\r
\r
bx r14\r
- nop\r
}\r
/*-----------------------------------------------------------*/\r
\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/* Configure SysTick to interrupt at the requested rate. */\r
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
}\r
\r
#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\r
/*-----------------------------------------------------------*/\r
\r
-__asm uint32_t ulPortSetInterruptMask( void )\r
-{\r
- PRESERVE8\r
-\r
- mrs r0, basepri\r
- mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
- msr basepri, r1\r
- bx r14\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__asm void vPortClearInterruptMask( uint32_t ulNewMask )\r
-{\r
- PRESERVE8\r
-\r
- msr basepri, r0\r
- bx r14\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
__asm uint32_t vPortGetIPSR( void )\r
{\r
PRESERVE8\r
projects / freertos / blobdiff