--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_hal_sd.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 26-June-2015\r
+ * @brief Header file of SD HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_HAL_SD_H\r
+#define __STM32F4xx_HAL_SD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_ll_sdmmc.h"\r
+\r
+/** @addtogroup STM32F4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SD SD\r
+ * @brief SD HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup SD_Exported_Types SD Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition\r
+ * @{\r
+ */\r
+#define SD_InitTypeDef SDIO_InitTypeDef\r
+#define SD_TypeDef SDIO_TypeDef\r
+\r
+struct xSD_Handle;\r
+\r
+/* A function will be called at the start of a DMA action. */\r
+typedef void ( * SD_EventSetupFunctionTypeDef )( struct xSD_Handle * /* pxhandle */ );\r
+\r
+/* This function is supposed to wait for an event: SDIO or DMA.\r
+ * Return non-zero if a timeout has been reached. */\r
+typedef uint32_t ( * SD_EventWaitFunctionTypeDef )( struct xSD_Handle * /* pxhandle */ );\r
+\r
+typedef struct xSD_Handle\r
+{\r
+ SD_TypeDef *Instance; /*!< SDIO register base address */\r
+\r
+ SD_InitTypeDef Init; /*!< SD required parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< SD locking object */\r
+\r
+ uint32_t CardType; /*!< SD card type */\r
+\r
+ uint32_t RCA; /*!< SD relative card address */\r
+\r
+ uint32_t CSD[4]; /*!< SD card specific data table */\r
+\r
+ uint32_t CID[4]; /*!< SD card identification number table */\r
+\r
+ __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */\r
+\r
+ __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */\r
+\r
+ __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */\r
+\r
+ __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */\r
+\r
+ SD_EventSetupFunctionTypeDef EventSetupFunction;\r
+\r
+ SD_EventWaitFunctionTypeDef EventWaitFunction;\r
+\r
+}SD_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint8_t CSDStruct; /*!< CSD structure */\r
+ __IO uint8_t SysSpecVersion; /*!< System specification version */\r
+ __IO uint8_t Reserved1; /*!< Reserved */\r
+ __IO uint8_t TAAC; /*!< Data read access time 1 */\r
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */\r
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */\r
+ __IO uint16_t CardComdClasses; /*!< Card command classes */\r
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */\r
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */\r
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */\r
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */\r
+ __IO uint8_t DSRImpl; /*!< DSR implemented */\r
+ __IO uint8_t Reserved2; /*!< Reserved */\r
+ __IO uint32_t DeviceSize; /*!< Device Size */\r
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */\r
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */\r
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */\r
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */\r
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */\r
+ __IO uint8_t EraseGrSize; /*!< Erase group size */\r
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */\r
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */\r
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */\r
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */\r
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */\r
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */\r
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */\r
+ __IO uint8_t Reserved3; /*!< Reserved */\r
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */\r
+ __IO uint8_t FileFormatGrouop; /*!< File format group */\r
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */\r
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */\r
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */\r
+ __IO uint8_t FileFormat; /*!< File format */\r
+ __IO uint8_t ECC; /*!< ECC code */\r
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */\r
+ __IO uint8_t Reserved4; /*!< Always 1 */\r
+\r
+}HAL_SD_CSDTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */\r
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */\r
+ __IO uint32_t ProdName1; /*!< Product Name part1 */\r
+ __IO uint8_t ProdName2; /*!< Product Name part2 */\r
+ __IO uint8_t ProdRev; /*!< Product Revision */\r
+ __IO uint32_t ProdSN; /*!< Product Serial Number */\r
+ __IO uint8_t Reserved1; /*!< Reserved1 */\r
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */\r
+ __IO uint8_t CID_CRC; /*!< CID CRC */\r
+ __IO uint8_t Reserved2; /*!< Always 1 */\r
+\r
+}HAL_SD_CIDTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */\r
+ __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */\r
+ __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */\r
+ __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */\r
+ __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */\r
+ __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */\r
+ __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */\r
+ __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */\r
+ __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */\r
+ __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */\r
+\r
+}HAL_SD_CardStatusTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group5 SD Card information structure\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */\r
+ HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */\r
+ uint64_t CardCapacity; /*!< Card capacity */\r
+ uint32_t CardBlockSize; /*!< Card block size */\r
+ uint16_t RCA; /*!< SD relative card address */\r
+ uint8_t CardType; /*!< SD card type */\r
+\r
+}HAL_SD_CardInfoTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+/**\r
+ * @brief SD specific error defines\r
+ */\r
+ SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */\r
+ SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */\r
+ SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */\r
+ SD_DATA_TIMEOUT = (4), /*!< Data timeout */\r
+ SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */\r
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */\r
+ SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */\r
+ SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */\r
+ SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */\r
+ SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */\r
+ SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */\r
+ SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */\r
+ SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */\r
+ SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */\r
+ SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */\r
+ SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */\r
+ SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */\r
+ SD_CC_ERROR = (18), /*!< Internal card controller error */\r
+ SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */\r
+ SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */\r
+ SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */\r
+ SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */\r
+ SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */\r
+ SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */\r
+ SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */\r
+ SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */\r
+ SD_INVALID_VOLTRANGE = (27),\r
+ SD_ADDR_OUT_OF_RANGE = (28),\r
+ SD_SWITCH_ERROR = (29),\r
+ SD_SDIO_DISABLED = (30),\r
+ SD_SDIO_FUNCTION_BUSY = (31),\r
+ SD_SDIO_FUNCTION_FAILED = (32),\r
+ SD_SDIO_UNKNOWN_FUNCTION = (33),\r
+\r
+/**\r
+ * @brief Standard error defines\r
+ */\r
+ SD_INTERNAL_ERROR = (34),\r
+ SD_NOT_CONFIGURED = (35),\r
+ SD_REQUEST_PENDING = (36),\r
+ SD_REQUEST_NOT_APPLICABLE = (37),\r
+ SD_INVALID_PARAMETER = (38),\r
+ SD_UNSUPPORTED_FEATURE = (39),\r
+ SD_UNSUPPORTED_HW = (40),\r
+ SD_ERROR = (41),\r
+ SD_OK = (0)\r
+\r
+}HAL_SD_ErrorTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ SD_TRANSFER_OK = 0, /*!< Transfer success */\r
+ SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */\r
+ SD_TRANSFER_ERROR = 2 /*!< Transfer failed */\r
+\r
+}HAL_SD_TransferStateTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */\r
+ SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */\r
+ SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */\r
+ SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */\r
+ SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */\r
+ SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */\r
+ SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */\r
+ SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */\r
+ SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */\r
+\r
+}HAL_SD_CardStateTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */\r
+ SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */\r
+ SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */\r
+ SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */\r
+\r
+}HAL_SD_OperationTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup SD_Exported_Constants SD Exported Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SD Commands Index\r
+ */\r
+#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */\r
+#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */\r
+#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */\r
+#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */\r
+#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */\r
+#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its\r
+ operating condition register (OCR) content in the response on the CMD line. */\r
+#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */\r
+#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */\r
+#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information\r
+ and asks the card whether card supports voltage. */\r
+#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */\r
+#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */\r
+#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */\r
+#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */\r
+#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */\r
+#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)\r
+#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */\r
+#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands\r
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective\r
+ for SDHS and SDXC. */\r
+#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of\r
+ fixed 512 bytes in case of SDHC and SDXC. */\r
+#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by\r
+ STOP_TRANSMISSION command. */\r
+#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */\r
+#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */\r
+#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */\r
+#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of\r
+ fixed 512 bytes in case of SDHC and SDXC. */\r
+#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */\r
+#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */\r
+#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */\r
+#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */\r
+#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */\r
+#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */\r
+#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */\r
+#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */\r
+#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command\r
+ system set by switch function command (CMD6). */\r
+#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.\r
+ Reserved for each command system set by switch function command (CMD6). */\r
+#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */\r
+#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */\r
+#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */\r
+#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by\r
+ the SET_BLOCK_LEN command. */\r
+#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather\r
+ than a standard command. */\r
+#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card\r
+ for general purpose/application specific commands. */\r
+#define SD_CMD_NO_CMD ((uint8_t)64)\r
+\r
+/**\r
+ * @brief Following commands are SD Card Specific commands.\r
+ * SDIO_APP_CMD should be sent before sending these commands.\r
+ */\r
+#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus\r
+ widths are given in SCR register. */\r
+#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */\r
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with\r
+ 32bit+CRC data block. */\r
+#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to\r
+ send its operating condition register (OCR) content in the response on the CMD line. */\r
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */\r
+#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */\r
+#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */\r
+#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */\r
+\r
+/**\r
+ * @brief Following commands are SD Card Specific security commands.\r
+ * SD_CMD_APP_CMD should be sent before sending these commands.\r
+ */\r
+#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */\r
+\r
+/**\r
+ * @brief Supported SD Memory Cards\r
+ */\r
+#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)\r
+#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)\r
+#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)\r
+#define MULTIMEDIA_CARD ((uint32_t)0x00000003)\r
+#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)\r
+#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)\r
+#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)\r
+#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup SD_Exported_macros SD Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the SD device.\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()\r
+\r
+/**\r
+ * @brief Disable the SD device.\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()\r
+\r
+/**\r
+ * @brief Enable the SDIO DMA transfer.\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()\r
+\r
+/**\r
+ * @brief Disable the SDIO DMA transfer.\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_DMA_DISABLE() __SDIO_DMA_DISABLE()\r
+\r
+/**\r
+ * @brief Enable the SD device interrupt.\r
+ * @param __HANDLE__: SD Handle\r
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide\r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the SD device interrupt.\r
+ * @param __HANDLE__: SD Handle\r
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide\r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified SD flag is set or not.\r
+ * @param __HANDLE__: SD Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress\r
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress\r
+ * @arg SDIO_FLAG_RXACT: Data receive in progress\r
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\r
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full\r
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full\r
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty\r
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty\r
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO\r
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval The new state of SD FLAG (SET or RESET).\r
+ */\r
+#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear the SD's pending flags.\r
+ * @param __HANDLE__: SD Handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))\r
+\r
+/**\r
+ * @brief Check whether the specified SD interrupt has occurred or not.\r
+ * @param __HANDLE__: SD Handle\r
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide\r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
+ * @retval The new state of SD IT (SET or RESET).\r
+ */\r
+#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)\r
+\r
+/**\r
+ * @brief Clear the SD's interrupt pending bits.\r
+ * @param __HANDLE__ : SD Handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide\r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SD_Exported_Functions SD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);\r
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);\r
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);\r
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Functions_Group2 I/O operation functions\r
+ * @{\r
+ */\r
+/* Blocking mode: Polling */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);\r
+\r
+/* Callback in non blocking modes (DMA) */\r
+void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);\r
+void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);\r
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);\r
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);\r
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);\r
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral State functions ************************************************/\r
+/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions\r
+ * @{\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);\r
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);\r
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup SD_Private_Types SD Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup SD_Private_Defines SD Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Variables SD Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Constants SD Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup SD_Private_Macros SD Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Functions SD Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_HAL_SD_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r