--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_hal_eth.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 26-June-2015\r
+ * @brief ETH HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Ethernet (ETH) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:\r
+ ETH_HandleTypeDef heth;\r
+\r
+ (#)Fill parameters of Init structure in heth handle\r
+\r
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)\r
+\r
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:\r
+ (##) Enable the Ethernet interface clock using\r
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();\r
+\r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure Ethernet pin-out\r
+ (##) Configure Ethernet NVIC interrupt (IT mode)\r
+\r
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:\r
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process\r
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process\r
+\r
+ (#)Enable MAC and DMA transmission and reception:\r
+ (##) HAL_ETH_Start();\r
+\r
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer\r
+ the frame to MAC TX FIFO:\r
+ (##) HAL_ETH_TransmitFrame();\r
+\r
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received\r
+ frame parameters\r
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)\r
+\r
+ (#) Get a received frame when an ETH RX interrupt occurs:\r
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)\r
+\r
+ (#) Communicate with external PHY device:\r
+ (##) Read a specific register from the PHY\r
+ HAL_ETH_ReadPHYRegister();\r
+ (##) Write data to a specific RHY register:\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ (#) Configure the Ethernet MAC after ETH peripheral initialization\r
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.\r
+\r
+ (#) Configure the Ethernet DMA after ETH peripheral initialization\r
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.\r
+\r
+ -@- The PTP protocol and the DMA descriptors ring mode are not supported\r
+ in this driver\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_hal.h"\r
+\r
+int lUDPLoggingPrintf( const char *pcFormatString, ... );\r
+\r
+/** @addtogroup STM32F4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH ETH\r
+ * @brief ETH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#if !defined( ARRAY_SIZE )\r
+ #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] )\r
+#endif\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+\r
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup ETH_Private_Constants ETH Private Constants\r
+ * @{\r
+ */\r
+#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */\r
+#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup ETH_Private_Functions ETH Private Functions\r
+ * @{\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ETH_Exported_Functions ETH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the Ethernet peripheral\r
+ (+) De-initialize the Ethernet peripheral\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+extern void vMACBProbePhy ( void );\r
+\r
+/**\r
+ * @brief Initializes the Ethernet MAC and DMA according to default\r
+ * parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ uint32_t hclk = 60000000;\r
+ uint32_t err = ETH_SUCCESS;\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth == NULL )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));\r
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));\r
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));\r
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));\r
+\r
+ if( heth->State == HAL_ETH_STATE_RESET )\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspInit( heth );\r
+ }\r
+\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ /* Select MII or RMII Mode*/\r
+ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);\r
+ SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;\r
+\r
+ /* Ethernet Software reset */\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ /* Also enable EDFE: Enhanced descriptor format enable. */\r
+ heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE;\r
+\r
+ /* Wait for software reset */\r
+ while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ }\r
+\r
+ /*-------------------------------- MAC Initialization ----------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tmpreg &= ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Get hclk frequency value (168,000,000) */\r
+ hclk = HAL_RCC_GetHCLKFreq();\r
+\r
+ /* Set CR bits depending on hclk value */\r
+ if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) )\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) )\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */\r
+ tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;\r
+ }\r
+ else if((hclk >= 60000000 ) && ( hclk < 100000000 ) )\r
+ {\r
+ /* CSR Clock Range between 60-100 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r
+ }\r
+ else if((hclk >= 100000000 ) && ( hclk < 150000000))\r
+ {\r
+ /* CSR Clock Range between 100-150 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r
+ }\r
+ else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */\r
+ {\r
+ /* CSR Clock Range between 150-168 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;\r
+ }\r
+\r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ heth->Instance->MACMIIAR = (uint32_t)tmpreg;\r
+\r
+ /* Initialise the MACB and set all PHY properties */\r
+ vMACBProbePhy();\r
+\r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the ETH peripheral.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspDeInit( heth );\r
+\r
+ /* Set ETH HAL state to Disabled */\r
+ heth->State= HAL_ETH_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMATxDescTab: Pointer to the first Tx desc list\r
+ * @param TxBuff: Pointer to the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the TxDesc pointer with the first one of the pxDMATable list */\r
+ heth->TxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for( i=0; i < ulBufferCount; i++ )\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable + i;\r
+\r
+ /* Set Second Address Chained bit */\r
+ pxDMADescriptor->Status = ETH_DMATXDESC_TCH;\r
+\r
+ pxDMADescriptor->ControlBufferSize = 0;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy transmissions. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */\r
+ pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < ( ulBufferCount - 1 ) )\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 );\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Transmit Descriptor List Address Register */\r
+ heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMARxDescTab: Pointer to the first Rx desc list\r
+ * @param RxBuff: Pointer to the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the RxDesc pointer with the first one of the pxDMATable list */\r
+ heth->RxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for(i=0; i < ulBufferCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable+i;\r
+\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ pxDMADescriptor->Status = ETH_DMARXDESC_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy reception. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE )\r
+ {\r
+ /* Enable Ethernet DMA Rx Descriptor interrupt */\r
+ pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (ulBufferCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Receive Descriptor List Address Register */\r
+ heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a frame\r
+ HAL_ETH_TransmitFrame();\r
+ (+) Receive a frame\r
+ HAL_ETH_GetReceivedFrame();\r
+ HAL_ETH_GetReceivedFrame_IT();\r
+ (+) Read from an External PHY register\r
+ HAL_ETH_ReadPHYRegister();\r
+ (+) Write to an External PHY register\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ @endverbatim\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an Ethernet frame.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param FrameLength: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r
+{\r
+ uint32_t bufcount = 0, size = 0, i = 0;\r
+ __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc;\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ if( FrameLength == 0 )\r
+ {\r
+ /* Set ETH HAL state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET )\r
+ {\r
+ /* OWN bit set */\r
+ heth->State = HAL_ETH_STATE_BUSY_TX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get the number of needed Tx buffers for the current frame, rounding up. */\r
+ bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE;\r
+\r
+ if (bufcount == 1)\r
+ {\r
+ /* Set LAST and FIRST segment */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;\r
+ /* Set frame size */\r
+ pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 );\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* Point to next descriptor */\r
+ heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ else\r
+ {\r
+ for( i = 0; i < bufcount; i++ )\r
+ {\r
+ /* Clear FIRST and LAST segment bits */\r
+ uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS );\r
+\r
+ if( i == 0 )\r
+ {\r
+ /* Setting the first segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS;\r
+ }\r
+\r
+ /* Program size */\r
+ if (i < (bufcount-1))\r
+ {\r
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r
+ }\r
+ else\r
+ {\r
+ /* Setting the last segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS;\r
+ size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r
+ }\r
+\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* point to next descriptor */\r
+ heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ }\r
+\r
+ __DSB();\r
+\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET )\r
+ {\r
+ heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc;\r
+\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ heth->Instance->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ heth->Instance->DMATPDR = 0;\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Checks for received frames.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth )\r
+{\r
+ return HAL_ETH_GetReceivedFrame( heth );\r
+}\r
+\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth )\r
+{\r
+uint32_t ulCounter = 0;\r
+ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc;\r
+HAL_StatusTypeDef xResult = HAL_ERROR;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Check the ETH state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Scan descriptors owned by CPU */\r
+ while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) )\r
+ {\r
+ uint32_t ulStatus = pxDescriptor->Status;\r
+\r
+ /* Just for security. */\r
+ ulCounter++;\r
+\r
+ if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS )\r
+ {\r
+ /* First segment in frame, but not the last. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL;\r
+ heth->RxFrameInfos.SegCount = 1;\r
+ /* Point to next descriptor. */\r
+ pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr);\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul )\r
+ {\r
+ /* This is an intermediate segment, not first, not last. */\r
+ /* Increment segment count. */\r
+ heth->RxFrameInfos.SegCount++;\r
+ /* Move to the next descriptor. */\r
+ pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr );\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ /* Must be a last segment */\r
+ else\r
+ {\r
+ /* This is the last segment. */\r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if( heth->RxFrameInfos.SegCount == 0 )\r
+ {\r
+ /* Remember the first segment. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ }\r
+\r
+ /* Increment segment count */\r
+ heth->RxFrameInfos.SegCount++;\r
+\r
+ /* Remember the last segment. */\r
+ heth->RxFrameInfos.LSRxDesc = pxDescriptor;\r
+\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ heth->RxFrameInfos.length =\r
+ ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;\r
+\r
+ /* Get the address of the buffer start address */\r
+ heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr;\r
+\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr;\r
+\r
+ /* Return OK status: a packet was received. */\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+#if( STM32_ETHERNET_STATS != 0 )\r
+\r
+ volatile int rx_count, tx_count, int_count;\r
+ /**\r
+ * @brief This function handles ETH interrupt request.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+ volatile int int_counts[32];\r
+ volatile int tx_status[8];\r
+ volatile unsigned sr_history[32];\r
+ volatile int sr_head;\r
+ #define STM32_STAT_INC( x ) do { ( x )++; } while( 0 )\r
+\r
+#else\r
+ #define STM32_STAT_INC( x ) do { } while( 0 )\r
+#endif /* STM32_ETHERNET_STATS */\r
+\r
+#define ETH_DMA_ALL_INTS \\r
+ ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \\r
+ ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \\r
+ ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )\r
+\r
+//#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS\r
+\r
+#define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) )\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t dmasr;\r
+\r
+ STM32_STAT_INC( int_count );\r
+\r
+ dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS;\r
+ heth->Instance->DMASR = dmasr;\r
+\r
+#if( STM32_ETHERNET_STATS != 0 )\r
+ if( sr_head < ARRAY_SIZE( sr_history ) )\r
+ {\r
+ sr_history[ sr_head++ ] = dmasr;\r
+ }\r
+\r
+ {\r
+ int i;\r
+ for (i = 0; i < 32; i++) {\r
+ if (dmasr & (1u << i)) {\r
+ int_counts[i]++;\r
+ }\r
+ }\r
+ tx_status[ ( dmasr >> 20 ) & 0x07 ]++;\r
+ }\r
+#endif\r
+\r
+ /* Frame received */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 )\r
+ {\r
+ /* Receive complete callback */\r
+ HAL_ETH_RxCpltCallback( heth );\r
+ STM32_STAT_INC( rx_count );\r
+ }\r
+ /* Frame transmitted */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 )\r
+ {\r
+ /* Transfer complete callback */\r
+ HAL_ETH_TxCpltCallback( heth );\r
+ STM32_STAT_INC( tx_count );\r
+ }\r
+\r
+ /* ETH DMA Error */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 )\r
+ {\r
+ /* Ethernet Error callback */\r
+ HAL_ETH_ErrorCallback( heth );\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Ethernet transfer error callbacks\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Reads a PHY register\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Basic Control Register,\r
+ * PHY_BSR: Transceiver Basic Status Register.\r
+ * More PHY register could be read depending on the used PHY\r
+ * @param RegValue: PHY register value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_RD )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_RD */\r
+ heth->State = HAL_ETH_STATE_BUSY_RD;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII address register value */\r
+ tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ /* Get MACMIIDR value */\r
+ *RegValue = ( uint32_t ) heth->Instance->MACMIIDR;\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ if( xResult != HAL_OK )\r
+ {\r
+ lUDPLoggingPrintf( "ReadPHY: %d\n", xResult );\r
+ }\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @brief Writes to a PHY register.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Control Register.\r
+ * More PHY register could be written depending on the used PHY\r
+ * @param RegValue: the value to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) );\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_WR )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_WR */\r
+ heth->State = HAL_ETH_STATE_BUSY_WR;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII register address value */\r
+ tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Give the value to the MII data register */\r
+ heth->Instance->MACMIIDR = ( uint16_t ) RegValue;\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ if( xResult != HAL_OK )\r
+ {\r
+ lUDPLoggingPrintf( "WritePHY: %d\n", xResult );\r
+ }\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Enable MAC and DMA transmission and reception.\r
+ HAL_ETH_Start();\r
+ (+) Disable MAC and DMA transmission and reception.\r
+ HAL_ETH_Stop();\r
+ (+) Set the MAC configuration in runtime mode\r
+ HAL_ETH_ConfigMAC();\r
+ (+) Set the DMA configuration in runtime mode\r
+ HAL_ETH_ConfigDMA();\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Enables Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth )\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Enable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionEnable( heth );\r
+\r
+ /* Enable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionEnable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionEnable( heth );\r
+\r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionEnable( heth );\r
+\r
+ /* Set the ETH state to READY*/\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Stop DMA transmission */\r
+ ETH_DMATransmissionDisable( heth );\r
+\r
+ /* Stop DMA reception */\r
+ ETH_DMAReceptionDisable( heth );\r
+\r
+ /* Disable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionDisable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Disable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionDisable( heth );\r
+\r
+ /* Set the ETH state*/\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACFCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACFCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACFCR = ulValue;\r
+}\r
+\r
+static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->DMAOMR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->DMAOMR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->DMAOMR = ulValue;\r
+}\r
+\r
+static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACCR = ulValue;\r
+}\r
+\r
+/**\r
+ * @brief Set ETH MAC Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param macconf: MAC Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));\r
+\r
+ if (macconf != NULL)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));\r
+ assert_param(IS_ETH_JABBER(macconf->Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));\r
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));\r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ macconf->Watchdog |\r
+ macconf->Jabber |\r
+ macconf->InterFrameGap |\r
+ macconf->CarrierSense |\r
+ heth->Init.Speed |\r
+ macconf->ReceiveOwn |\r
+ macconf->LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macconf->ChecksumOffload |\r
+ macconf->RetryTransmission |\r
+ macconf->AutomaticPadCRCStrip |\r
+ macconf->BackOffLimit |\r
+ macconf->DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(\r
+ macconf->ReceiveAll |\r
+ macconf->SourceAddrFilter |\r
+ macconf->PassControlFrames |\r
+ macconf->BroadcastFramesReception |\r
+ macconf->DestinationAddrFilter |\r
+ macconf->PromiscuousMode |\r
+ macconf->MulticastFramesFilter |\r
+ macconf->UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)((\r
+ macconf->PauseTime << 16) |\r
+ macconf->ZeroQuantaPause |\r
+ macconf->PauseLowThreshold |\r
+ macconf->UnicastPauseFrameDetect |\r
+ macconf->ReceiveFlowControl |\r
+ macconf->TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |\r
+ macconf->VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+ }\r
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */\r
+ {\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+\r
+ /* Clear FES and DM bits */\r
+ tmpreg &= ~((uint32_t)0x00004800);\r
+\r
+ tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+ }\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets ETH DMA Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param dmaconf: DMA Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));\r
+ assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));\r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));\r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));\r
+\r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ dmaconf->DropTCPIPChecksumErrorFrame |\r
+ dmaconf->ReceiveStoreForward |\r
+ dmaconf->FlushReceivedFrame |\r
+ dmaconf->TransmitStoreForward |\r
+ dmaconf->TransmitThresholdControl |\r
+ dmaconf->ForwardErrorFrames |\r
+ dmaconf->ForwardUndersizedGoodFrames |\r
+ dmaconf->ReceiveThresholdControl |\r
+ dmaconf->SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/\r
+ heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |\r
+ dmaconf->FixedBurst |\r
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmaconf->TxDMABurstLength |\r
+ dmaconf->EnhancedDescriptorFormat |\r
+ (dmaconf->DescriptorSkipLength << 2) |\r
+ dmaconf->DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+ (+) Get the ETH handle state:\r
+ HAL_ETH_GetState();\r
+\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the ETH HAL state\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL state\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Return ETH state */\r
+ return heth->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures Ethernet MAC and DMA with default parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param err: Ethernet Init error\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)\r
+{\r
+ ETH_MACInitTypeDef macinit;\r
+ ETH_DMAInitTypeDef dmainit;\r
+ uint32_t tmpreg = 0;\r
+\r
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex */\r
+ heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
+\r
+ /* Set Ethernet speed to 100M */\r
+ heth->Init.Speed = ETH_SPEED_100M;\r
+ }\r
+\r
+ /* Ethernet MAC default initialization **************************************/\r
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;\r
+ macinit.Jabber = ETH_JABBER_ENABLE;\r
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;\r
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;\r
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;\r
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;\r
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;\r
+ }\r
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;\r
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;\r
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;\r
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;\r
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;\r
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;\r
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;\r
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;\r
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;\r
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r
+ macinit.HashTableHigh = 0x0;\r
+ macinit.HashTableLow = 0x0;\r
+ macinit.PauseTime = 0x0;\r
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r
+ macinit.VLANTagIdentifier = 0x0;\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH Watchdog value */\r
+ /* Set the JD: bit according to ETH Jabber value */\r
+ /* Set the IFG bit according to ETH InterFrameGap value */\r
+ /* Set the DCRS bit according to ETH CarrierSense value */\r
+ /* Set the FES bit according to ETH Speed value */\r
+ /* Set the DO bit according to ETH ReceiveOwn value */\r
+ /* Set the LM bit according to ETH LoopbackMode value */\r
+ /* Set the DM bit according to ETH Mode value */\r
+ /* Set the IPCO bit according to ETH ChecksumOffload value */\r
+ /* Set the DR bit according to ETH RetryTransmission value */\r
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */\r
+ /* Set the BL bit according to ETH BackOffLimit value */\r
+ /* Set the DC bit according to ETH DeferralCheck value */\r
+ tmpreg |= (uint32_t)(macinit.Watchdog |\r
+ macinit.Jabber |\r
+ macinit.InterFrameGap |\r
+ macinit.CarrierSense |\r
+ heth->Init.Speed |\r
+ macinit.ReceiveOwn |\r
+ macinit.LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macinit.ChecksumOffload |\r
+ macinit.RetryTransmission |\r
+ macinit.AutomaticPadCRCStrip |\r
+ macinit.BackOffLimit |\r
+ macinit.DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Set the RA bit according to ETH ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH PassControlFrames value */\r
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll |\r
+ macinit.SourceAddrFilter |\r
+ macinit.PassControlFrames |\r
+ macinit.BroadcastFramesReception |\r
+ macinit.DestinationAddrFilter |\r
+ macinit.PromiscuousMode |\r
+ macinit.MulticastFramesFilter |\r
+ macinit.UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ /* Set the PT bit according to ETH PauseTime value */\r
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH TransmitFlowControl value */\r
+ tmpreg |= (uint32_t)((macinit.PauseTime << 16) |\r
+ macinit.ZeroQuantaPause |\r
+ macinit.PauseLowThreshold |\r
+ macinit.UnicastPauseFrameDetect |\r
+ macinit.ReceiveFlowControl |\r
+ macinit.TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/\r
+ /* Set the ETV bit according to ETH VLANTagComparison value */\r
+ /* Set the VL bit according to ETH VLANTagIdentifier value */\r
+ heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |\r
+ macinit.VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+\r
+ /* Ethernet DMA default initialization ************************************/\r
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;\r
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;\r
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;\r
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;\r
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;\r
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;\r
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;\r
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;\r
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;\r
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r
+ dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r
+ dmainit.DescriptorSkipLength = 0x0;\r
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r
+\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |\r
+ dmainit.ReceiveStoreForward |\r
+ dmainit.FlushReceivedFrame |\r
+ dmainit.TransmitStoreForward |\r
+ dmainit.TransmitThresholdControl |\r
+ dmainit.ForwardErrorFrames |\r
+ dmainit.ForwardUndersizedGoodFrames |\r
+ dmainit.ReceiveThresholdControl |\r
+ dmainit.SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/\r
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */\r
+ /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/\r
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH DMAArbitration value */\r
+ heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |\r
+ dmainit.FixedBurst |\r
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmainit.TxDMABurstLength |\r
+ dmainit.EnhancedDescriptorFormat |\r
+ (dmainit.DescriptorSkipLength << 2) |\r
+ dmainit.DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable the Ethernet Rx Interrupt */\r
+ __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R);\r
+ }\r
+\r
+ /* Initialize MAC address in ethernet MAC */\r
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param MacAddr: The MAC address to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0: MAC Address0\r
+ * @arg ETH_MAC_Address1: MAC Address1\r
+ * @arg ETH_MAC_Address2: MAC Address2\r
+ * @arg ETH_MAC_Address3: MAC Address3\r
+ * @param Addr: Pointer to MAC address buffer data (6 bytes)\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ /* Check the parameters */\r
+ assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );\r
+\r
+ /* Calculate the selected MAC address high register */\r
+ tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];\r
+ /* Load the selected MAC address high register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;\r
+ /* Calculate the selected MAC address low register */\r
+ tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ];\r
+\r
+ /* Load the selected MAC address low register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the Flush Transmit FIFO bit */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r