/*******************************************************************************\r
- * Tracealyzer v3.0.2 Recorder Library\r
+ * Trace Recorder Library for Tracealyzer v3.1.2\r
* Percepio AB, www.percepio.com\r
*\r
* trcHardwarePort.h\r
*\r
- * Contains together with trcHardwarePort.c all hardware portability issues of\r
- * the trace recorder library.\r
+ * The hardware abstraction layer for the trace recorder.\r
*\r
* Terms of Use\r
- * This software is copyright Percepio AB. The recorder library is free for\r
- * use together with Percepio products. You may distribute the recorder library\r
- * in its original form, including modifications in trcPort.c and trcPort.h\r
- * given that these modification are clearly marked as your own modifications\r
- * and documented in the initial comment section of these source files.\r
- * This software is the intellectual property of Percepio AB and may not be\r
- * sold or in other ways commercially redistributed without explicit written\r
- * permission by Percepio AB.\r
+ * This file is part of the trace recorder library (RECORDER), which is the \r
+ * intellectual property of Percepio AB (PERCEPIO) and provided under a\r
+ * license as follows.\r
+ * The RECORDER may be used free of charge for the purpose of recording data\r
+ * intended for analysis in PERCEPIO products. It may not be used or modified\r
+ * for other purposes without explicit permission from PERCEPIO.\r
+ * You may distribute the RECORDER in its original source code form, assuming\r
+ * this text (terms of use, disclaimer, copyright notice) is unchanged. You are\r
+ * allowed to distribute the RECORDER with minor modifications intended for\r
+ * configuration or porting of the RECORDER, e.g., to allow using it on a \r
+ * specific processor, processor family or with a specific communication\r
+ * interface. Any such modifications should be documented directly below\r
+ * this comment block.\r
*\r
* Disclaimer\r
- * The trace tool and recorder library is being delivered to you AS IS and\r
- * Percepio AB makes no warranty as to its use or performance. Percepio AB does\r
- * not and cannot warrant the performance or results you may obtain by using the\r
- * software or documentation. Percepio AB make no warranties, express or\r
- * implied, as to noninfringement of third party rights, merchantability, or\r
- * fitness for any particular purpose. In no event will Percepio AB, its\r
- * technology partners, or distributors be liable to you for any consequential,\r
- * incidental or special damages, including any lost profits or lost savings,\r
- * even if a representative of Percepio AB has been advised of the possibility\r
- * of such damages, or for any claim by any third party. Some jurisdictions do\r
- * not allow the exclusion or limitation of incidental, consequential or special\r
- * damages, or the exclusion of implied warranties or limitations on how long an\r
- * implied warranty may last, so the above limitations may not apply to you.\r
+ * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty\r
+ * as to its use or performance. PERCEPIO does not and cannot warrant the \r
+ * performance or results you may obtain by using the RECORDER or documentation.\r
+ * PERCEPIO make no warranties, express or implied, as to noninfringement of\r
+ * third party rights, merchantability, or fitness for any particular purpose.\r
+ * In no event will PERCEPIO, its technology partners, or distributors be liable\r
+ * to you for any consequential, incidental or special damages, including any\r
+ * lost profits or lost savings, even if a representative of PERCEPIO has been\r
+ * advised of the possibility of such damages, or for any claim by any third\r
+ * party. Some jurisdictions do not allow the exclusion or limitation of\r
+ * incidental, consequential or special damages, or the exclusion of implied\r
+ * warranties or limitations on how long an implied warranty may last, so the\r
+ * above limitations may not apply to you.\r
*\r
* Tabs are used for indent in this file (1 tab = 4 spaces)\r
*\r
- * Copyright Percepio AB, 2014.\r
+ * Copyright Percepio AB, 2017.\r
* www.percepio.com\r
******************************************************************************/\r
\r
-#ifndef TRCPORT_H\r
-#define TRCPORT_H\r
-#include <stdint.h>\r
+#ifndef TRC_HARDWARE_PORT_H\r
+#define TRC_HARDWARE_PORT_H\r
\r
-/* If Win32 port */\r
-#ifdef WIN32\r
+#include "trcPortDefines.h"\r
\r
- /* Standard includes. */\r
- #include <stdio.h>\r
- #include <windows.h>\r
- #include <direct.h>\r
-\r
-/*******************************************************************************\r
- * The Win32 port by default saves the trace to file and then kills the\r
- * program when the recorder is stopped, to facilitate quick, simple tests\r
- * of the recorder.\r
- ******************************************************************************/\r
- #define WIN32_PORT_SAVE_WHEN_STOPPED 1\r
- #define WIN32_PORT_EXIT_WHEN_STOPPED 1\r
\r
+#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)\r
+ #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"\r
#endif\r
\r
-#define DIRECTION_INCREMENTING 1\r
-#define DIRECTION_DECREMENTING 2\r
-\r
-/******************************************************************************\r
- * Supported ports\r
- *\r
- * PORT_HWIndependent\r
- * A hardware independent fallback option for event timestamping. Provides low\r
- * resolution timestamps based on the OS tick.\r
- * This may be used on the Win32 port, but may also be used on embedded hardware\r
- * platforms. All time durations will be truncated to the OS tick frequency,\r
- * typically 1 KHz. This means that a task or ISR that executes in less than\r
- * 1 ms get an execution time of zero.\r
- *\r
- * PORT_APPLICATION_DEFINED\r
- * Allows for defining the port macros in other source code files.\r
- *\r
- * PORT_Win32\r
- * "Accurate" timestamping based on the Windows performance counter for Win32\r
- * builds. Note that this gives the host machine time, not the kernel time.\r
- *\r
- * Hardware specific ports\r
- * To get accurate timestamping, a hardware timer is necessary. Below are the\r
- * available ports. Some of these are "unofficial", meaning that\r
- * they have not yet been verified by Percepio but have been contributed by\r
- * external developers. They should work, otherwise let us know by emailing\r
- * support@percepio.com. Some work on any OS platform, while other are specific\r
- * to a certain operating system.\r
- *****************************************************************************/\r
-\r
-/****** Port Name ********************** Code ***** Official ** OS Platform *********/\r
-#define PORT_APPLICATION_DEFINED -2 /* - - */\r
-#define PORT_NOT_SET -1 /* - - */\r
-#define PORT_HWIndependent 0 /* Yes Any */\r
-#define PORT_Win32 1 /* Yes FreeRTOS on Win32 */\r
-#define PORT_Atmel_AT91SAM7 2 /* No Any */\r
-#define PORT_Atmel_UC3A0 3 /* No Any */\r
-#define PORT_ARM_CortexM 4 /* Yes Any */\r
-#define PORT_Renesas_RX600 5 /* Yes Any */\r
-#define PORT_Microchip_dsPIC_AND_PIC24 6 /* Yes Any */\r
-#define PORT_TEXAS_INSTRUMENTS_TMS570 7 /* No Any */\r
-#define PORT_TEXAS_INSTRUMENTS_MSP430 8 /* No Any */\r
-#define PORT_MICROCHIP_PIC32MX 9 /* Yes Any */\r
-#define PORT_XILINX_PPC405 10 /* No FreeRTOS */\r
-#define PORT_XILINX_PPC440 11 /* No FreeRTOS */\r
-#define PORT_XILINX_MICROBLAZE 12 /* No Any */\r
-#define PORT_NXP_LPC210X 13 /* No Any */\r
-#define PORT_MICROCHIP_PIC32MZ 14 /* Yes Any */\r
-#define PORT_ARM_CORTEX_A9 15 /* No Any */\r
-#define PORT_ARM_CORTEX_M0 16 /* Yes Any */\r
-\r
-#include "trcConfig.h"\r
-\r
/*******************************************************************************\r
- * IRQ_PRIORITY_ORDER\r
+ * TRC_IRQ_PRIORITY_ORDER\r
*\r
* Macro which should be defined as an integer of 0 or 1.\r
*\r
*\r
* HWTC Macros\r
*\r
- * These four HWTC macros provides a hardware isolation layer representing a\r
- * generic hardware timer/counter used for driving the operating system tick,\r
- * such as the SysTick feature of ARM Cortex M3/M4, or the PIT of the Atmel\r
- * AT91SAM7X.\r
+ * These macros provides a hardware isolation layer representing the\r
+ * hardware timer/counter used for the event timestamping.\r
+ *\r
+ * TRC_HWTC_COUNT: How to read the current value of the timer/counter.\r
+ *\r
+ * TRC_HWTC_TYPE: Tells the type of timer/counter used for TRC_HWTC_COUNT:\r
*\r
- * HWTC_COUNT: The current value of the counter. This is expected to be reset\r
- * a each tick interrupt. Thus, when the tick handler starts, the counter has\r
- * already wrapped.\r
+ * - TRC_FREE_RUNNING_32BIT_INCR:\r
+ * Free-running 32-bit timer/counter, counting upwards from 0.\r
*\r
- * HWTC_COUNT_DIRECTION: Should be one of:\r
- * - DIRECTION_INCREMENTING - for hardware timer/counters of incrementing type\r
- * such as the PIT on Atmel AT91SAM7X.\r
- * When the counter value reach HWTC_PERIOD, it is reset to zero and the\r
- * interrupt is signaled.\r
- * - DIRECTION_DECREMENTING - for hardware timer/counters of decrementing type\r
- * such as the SysTick on ARM Cortex M3/M4 chips.\r
- * When the counter value reach 0, it is reset to HWTC_PERIOD and the\r
- * interrupt is signaled.\r
+ * - TRC_FREE_RUNNING_32BIT_DECR\r
+ * Free-running 32-bit timer/counter, counting downwards from 0xFFFFFFFF.\r
*\r
- * HWTC_PERIOD: The number of increments or decrements of HWTC_COUNT between\r
- * two OS tick interrupts. This should preferably be mapped to the reload\r
- * register of the hardware timer, to make it more portable between chips in the\r
- * same family. The macro should in most cases be (reload register + 1).\r
- * For FreeRTOS, this can in most cases be defined as\r
- * #define HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ)\r
+ * - TRC_OS_TIMER_INCR\r
+ * Periodic timer that drives the OS tick interrupt, counting upwards\r
+ * from 0 until (TRC_HWTC_PERIOD-1).\r
*\r
- * HWTC_DIVISOR: If the timer frequency is very high, like on the Cortex M chips\r
- * (where the SysTick runs at the core clock frequency), the "differential\r
- * timestamping" used in the recorder will more frequently insert extra XTS\r
- * events to store the timestamps, which increases the event buffer usage.\r
- * In such cases, to reduce the number of XTS events and thereby get longer\r
- * traces, you use HWTC_DIVISOR to scale down the timestamps and frequency.\r
- * Assuming a OS tick rate of 1 KHz, it is suggested to keep the effective timer\r
- * frequency below 65 MHz to avoid an excessive amount of XTS events. Thus, a\r
- * Cortex M chip running at 72 MHZ should use a HWTC_DIVISOR of 2, while a\r
- * faster chip require a higher HWTC_DIVISOR value.\r
+ * - TRC_OS_TIMER_DECR\r
+ * Periodic timer that drives the OS tick interrupt, counting downwards\r
+ * from TRC_HWTC_PERIOD-1 until 0.\r
*\r
- * The HWTC macros and vTracePortGetTimeStamp is the main porting issue\r
- * or the trace recorder library. Typically you should not need to change\r
- * the code of vTracePortGetTimeStamp if using the HWTC macros.\r
+ * - TRC_CUSTOM_TIMER_INCR\r
+ * A custom timer or counter independent of the OS tick, counting\r
+ * downwards from TRC_HWTC_PERIOD-1 until 0. (Currently only supported\r
+ * in streaming mode).\r
*\r
+ * - TRC_CUSTOM_TIMER_DECR\r
+ * A custom timer independent of the OS tick, counting downwards\r
+ * from TRC_HWTC_PERIOD-1 until 0. (Currently only supported\r
+ * in streaming mode).\r
+ *\r
+ * TRC_HWTC_PERIOD: The number of HWTC_COUNT ticks until the timer wraps\r
+ * around. If using TRC_FREE_RUNNING_32BIT_INCR/DECR, this should be 0. \r
+ *\r
+ * TRC_HWTC_FREQ_HZ: The clock rate of the TRC_HWTC_COUNT counter in Hz. If using \r
+ * TRC_OS_TIMER_INCR/DECR, this is should be TRC_HWTC_PERIOD * TRACE_TICK_RATE_HZ.\r
+ * If using a free-running timer, this is often TRACE_CPU_CLOCK_HZ (if running at\r
+ * the core clock rate). If using TRC_CUSTOM_TIMER_INCR/DECR, this should match\r
+ * the clock rate of your custom timer (i.e., TRC_HWTC_COUNT). If the default value\r
+ * of TRC_HWTC_FREQ_HZ is incorrect for your setup, you can override it by calling\r
+ * vTraceSetFrequency before calling vTraceEnable.\r
+ *\r
+ * TRC_HWTC_DIVISOR (used in snapshot mode only):\r
+ * In snapshot mode, the timestamp resolution is TRC_HWTC_FREQ_HZ/TRC_HWTC_DIVISOR.\r
+ * If the timer frequency is very high (hundreds of MHz), we recommend increasing\r
+ * the TRC_HWTC_DIVISOR prescaler, to reduce the bandwidth needed to store\r
+ * timestamps. This since extra "XTS" events are inserted if the time since the\r
+ * previous event exceeds a certain limit (255 or 65535 depending on event type).\r
+ * It is advised to keep the time between most events below 65535 native ticks\r
+ * (after division by TRC_HWTC_DIVISOR) to avoid frequent XTS events.\r
******************************************************************************/\r
\r
-#if (SELECTED_PORT == PORT_Win32)\r
- // This can be used as a template for any free-running 32-bit counter\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT (ulGetRunTimeCounterValue())\r
- #define HWTC_PERIOD 0\r
- #define HWTC_DIVISOR 1\r
-\r
- // Please update according to your system...\r
- #define IRQ_PRIORITY_ORDER 1\r
-\r
-#elif (SELECTED_PORT == PORT_HWIndependent)\r
- // OS Tick only (typically 1 ms resolution)\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT 0\r
- #define HWTC_PERIOD 1\r
- #define HWTC_DIVISOR 1\r
-\r
- // Please update according to your system...\r
- #define IRQ_PRIORITY_ORDER NOT_SET\r
-\r
-\r
-#elif (SELECTED_PORT == PORT_ARM_CortexM)\r
-\r
- void prvTraceInitCortexM(void);\r
-\r
- #define REG_DEMCR (*(volatile unsigned int*)0xE000EDFC)\r
- #define REG_DWT_CTRL (*(volatile unsigned int*)0xE0001000)\r
- #define REG_DWT_CYCCNT (*(volatile unsigned int*)0xE0001004)\r
- #define REG_DWT_EXCCNT (*(volatile unsigned int*)0xE000100C)\r
-\r
- /* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */\r
- #define DEMCR_TRCENA (1 << 24)\r
-\r
- /* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */\r
- #define DWT_CTRL_NOPRFCNT (1 << 24)\r
-\r
- /* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */\r
- #define DWT_CTRL_NOCYCCNT (1 << 25)\r
-\r
- /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */\r
- #define DWT_CTRL_EXCEVTENA (1 << 18)\r
-\r
- /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */\r
- #define DWT_CTRL_CYCCNTENA (1)\r
-\r
- #define PORT_SPECIFIC_INIT() prvTraceInitCortexM()\r
-\r
- extern uint32_t DWT_CYCLES_ADDED;\r
-\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT (REG_DWT_CYCCNT + DWT_CYCLES_ADDED)\r
- #define HWTC_PERIOD 0\r
- #define HWTC_DIVISOR 4\r
-\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
+#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)\r
+ #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"\r
+#endif\r
\r
-#elif (SELECTED_PORT == PORT_ARM_CORTEX_M0)\r
- #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING\r
- #define HWTC_COUNT (*((uint32_t*)0xE000E018))\r
- #define HWTC_PERIOD ((*(uint32_t*)0xE000E014) + 1)\r
- #define HWTC_DIVISOR 2\r
+#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32)\r
+ /* This can be used as a template for any free-running 32-bit counter */\r
+ #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR\r
+ #define TRC_HWTC_COUNT (ulGetRunTimeCounterValue())\r
+ #define TRC_HWTC_PERIOD 0\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ 100000\r
+ \r
+ #define TRC_IRQ_PRIORITY_ORDER 1\r
+\r
+ #define TRC_PORT_SPECIFIC_INIT()\r
+\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_HWIndependent)\r
+ /* Timestamping by OS tick only (typically 1 ms resolution) */\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT 0\r
+ #define TRC_HWTC_PERIOD 1\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ TRACE_TICK_RATE_HZ\r
+\r
+ /* Set the meaning of IRQ priorities in ISR tracing - see above */\r
+ #define TRC_IRQ_PRIORITY_ORDER NOT_SET\r
+\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M)\r
+ \r
+ #ifndef __CORTEX_M\r
+ #error "Can't find the CMSIS API. Please include your processor's header file in trcConfig.h" \r
+ #endif\r
\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
+ /**************************************************************************\r
+ * For Cortex-M3, M4 and M7, the DWT cycle counter is used for timestamping.\r
+ * For Cortex-M0 and M0+, the SysTick timer is used since DWT is not\r
+ * available. Systick timestamping can also be forced on Cortex-M3, M4 and\r
+ * M7 by defining the preprocessor directive TRC_CFG_ARM_CM_USE_SYSTICK,\r
+ * either directly below or in trcConfig.h.\r
+ *\r
+ * #define TRC_CFG_ARM_CM_USE_SYSTICK\r
+ **************************************************************************/\r
+\r
+ #if ((__CORTEX_M >= 0x03) && (! defined TRC_CFG_ARM_CM_USE_SYSTICK))\r
+ \r
+ void prvTraceInitCortexM(void);\r
+\r
+ #define TRC_REG_DEMCR (*(volatile uint32_t*)0xE000EDFC)\r
+ #define TRC_REG_DWT_CTRL (*(volatile uint32_t*)0xE0001000)\r
+ #define TRC_REG_DWT_CYCCNT (*(volatile uint32_t*)0xE0001004)\r
+ #define TRC_REG_DWT_EXCCNT (*(volatile uint32_t*)0xE000100C)\r
+\r
+ #define TRC_REG_ITM_LOCKACCESS (*(volatile uint32_t*)0xE0001FB0) \r
+ #define TRC_ITM_LOCKACCESS_UNLOCK (0xC5ACCE55)\r
+ \r
+ /* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */\r
+ #define TRC_DEMCR_TRCENA (1 << 24)\r
+\r
+ /* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */\r
+ #define TRC_DWT_CTRL_NOPRFCNT (1 << 24)\r
+\r
+ /* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */\r
+ #define TRC_DWT_CTRL_NOCYCCNT (1 << 25)\r
+\r
+ /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */\r
+ #define TRC_DWT_CTRL_EXCEVTENA (1 << 18)\r
+\r
+ /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */\r
+ #define TRC_DWT_CTRL_CYCCNTENA (1)\r
+\r
+ #define TRC_PORT_SPECIFIC_INIT() prvTraceInitCortexM()\r
+\r
+ #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR\r
+ #define TRC_HWTC_COUNT TRC_REG_DWT_CYCCNT\r
+ #define TRC_HWTC_PERIOD 0\r
+ #define TRC_HWTC_DIVISOR 4\r
+ #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
+ \r
+ #else\r
+ \r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR\r
+ #define TRC_HWTC_COUNT (*((volatile uint32_t*)0xE000E018))\r
+ #define TRC_HWTC_PERIOD ((*((volatile uint32_t*)0xE000E014)) + 1)\r
+ #define TRC_HWTC_DIVISOR 4\r
+ #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
+ \r
+ #endif\r
\r
-#elif (SELECTED_PORT == PORT_Renesas_RX600)\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600)\r
\r
#include "iodefine.h"\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT (CMT0.CMCNT)\r
- #define HWTC_PERIOD (CMT0.CMCOR + 1)\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant\r
-\r
-#elif ((SELECTED_PORT == PORT_MICROCHIP_PIC32MX) || (SELECTED_PORT == PORT_MICROCHIP_PIC32MZ))\r
-\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT (TMR1)\r
- #define HWTC_PERIOD (PR1 + 1)\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
-\r
-#elif (SELECTED_PORT == PORT_Microchip_dsPIC_AND_PIC24)\r
-\r
- /* For Microchip PIC24 and dsPIC (16 bit) */\r
-\r
- /* Note: The trace library is designed for 32-bit MCUs and is slower than\r
- intended on 16-bit MCUs. Storing an event on a PIC24 takes about 70 usec.\r
- In comparison, this is 10-20 times faster on a 32-bit MCU... */\r
+ #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) \r
+ \r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT (CMT0.CMCNT)\r
+ \r
+ #elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)\r
+ \r
+ /* Decreasing counters better for Tickless Idle? */\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR\r
+ #define TRC_HWTC_COUNT (CMT0.CMCOR - CMT0.CMCNT)\r
+ \r
+ #endif\r
+ \r
+ #define TRC_HWTC_PERIOD (CMT0.CMCOR + 1)\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 1 \r
+ \r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32)\r
+\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT (TMR1)\r
+ #define TRC_HWTC_PERIOD (PR1 + 1)\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
+\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48)\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT (TMR1)\r
- #define HWTC_PERIOD (PR1+1)\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
+ #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)\r
+ #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)\r
+ #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)\r
+ \r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))\r
+ #define TRC_HWTC_PERIOD (TRC_RTIUDCP0)\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
\r
-#elif (SELECTED_PORT == PORT_Atmel_AT91SAM7)\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_AT91SAM7)\r
\r
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))\r
- #define HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))\r
+ #define TRC_HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 1\r
\r
-#elif (SELECTED_PORT == PORT_Atmel_UC3A0)\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_UC3A0)\r
\r
- /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
- /* For Atmel AVR32 (AT32UC3A).*/\r
+ /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO*/\r
+ \r
+ /* For Atmel AVR32 (AT32UC3A) */\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))\r
- #define HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))\r
+ #define TRC_HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 1\r
\r
-#elif (SELECTED_PORT == PORT_NXP_LPC210X)\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NXP_LPC210X)\r
\r
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
+ \r
/* Tested with LPC2106, but should work with most LPC21XX chips. */\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT *((uint32_t *)0xE0004008 )\r
- #define HWTC_PERIOD *((uint32_t *)0xE0004018 )\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT *((uint32_t *)0xE0004008 )\r
+ #define TRC_HWTC_PERIOD *((uint32_t *)0xE0004018 )\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
\r
-#elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_TMS570)\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430)\r
\r
- /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
+ /* UNOFFICIAL PORT - NOT YET VERIFIED */\r
+ \r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR\r
+ #define TRC_HWTC_COUNT (TA0R)\r
+ #define TRC_HWTC_PERIOD (((uint16_t)TACCR0)+1)\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 1\r
\r
- #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)\r
- #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)\r
- #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))\r
- #define HWTC_PERIOD (RTIUDCP0)\r
- #define HWTC_DIVISOR 1\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC405)\r
\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
+ /* UNOFFICIAL PORT - NOT YET VERIFIED */\r
+ \r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR\r
+ #define TRC_HWTC_COUNT mfspr(0x3db)\r
+ #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ)\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
\r
-#elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_MSP430)\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC440)\r
\r
- /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
+ /* UNOFFICIAL PORT */\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING\r
- #define HWTC_COUNT (TA0R)\r
- #define HWTC_PERIOD (((uint16_t)TACCR0)+1)\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant\r
-\r
-#elif (SELECTED_PORT == PORT_XILINX_PPC405)\r
-\r
- /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
-\r
- #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING\r
- #define HWTC_COUNT mfspr(0x3db)\r
- #if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS\r
- /* For FreeRTOS only - found no generic OS independent solution for the PPC405 architecture. */\r
- #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC405\r
- #else\r
- /* Not defined for other operating systems yet */\r
- #error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.\r
- #endif\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
-\r
-#elif (SELECTED_PORT == PORT_XILINX_PPC440)\r
-\r
- /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
/* This should work with most PowerPC chips */\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING\r
- #define HWTC_COUNT mfspr(0x016)\r
- #if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS\r
- /* For FreeRTOS only - found no generic OS independent solution for the PPC440 architecture. */\r
- #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC440\r
- #else\r
- /* Not defined for other operating systems yet */\r
- #error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.\r
- #endif\r
- #define HWTC_DIVISOR 1\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR\r
+ #define TRC_HWTC_COUNT mfspr(0x016)\r
+ #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ)\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
\r
-#elif (SELECTED_PORT == PORT_XILINX_MICROBLAZE)\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_MICROBLAZE)\r
\r
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
\r
* If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required.\r
*/\r
#include "xtmrctr_l.h"\r
+ \r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR\r
+ #define TRC_HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )\r
+ #define TRC_HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)\r
+ #define TRC_HWTC_DIVISOR 16\r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
+\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)\r
+ /* INPUT YOUR PERIPHERAL BASE ADDRESS HERE */\r
+ #define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0xSOMETHING\r
+ \r
+ #define TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600\r
+ #define TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00))\r
+ #define TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04))\r
+ #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08))\r
+ \r
+ #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00\r
+ #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8\r
+ #define TRC_CA9_MPCORE_PRIVCTR_PRESCALER (((TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG & TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)\r
+\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR\r
+ #define TRC_HWTC_COUNT TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG\r
+ #define TRC_HWTC_PERIOD (TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG + 1)\r
+\r
+ /****************************************************************************************\r
+ NOTE: The private timer ticks with a very high frequency (half the core-clock usually), \r
+ depending on the prescaler used. If a low prescaler is used, the number of HW ticks between\r
+ the trace events gets large, and thereby inefficient to store (sometimes extra events are\r
+ needed). To improve efficiency, you may use the TRC_HWTC_DIVISOR as an additional prescaler.\r
+ *****************************************************************************************/ \r
+ #define TRC_HWTC_DIVISOR 1\r
+ \r
+ #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
+ #define TRC_IRQ_PRIORITY_ORDER 0\r
+\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4)\r
+\r
+ /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
+\r
+ #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR\r
+ //#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING\r
+ #define TRC_HWTC_COUNT PIT.TIMER[configTICK_PIT_CHANNEL].CVAL.R // must be the PIT channel used for the systick\r
+ #define TRC_HWTC_PERIOD ((configPIT_CLOCK_HZ / configTICK_RATE_HZ) - 1U) // TODO FIXME or maybe not -1? what's the right "period" value?\r
+ #define TRC_HWTC_FREQ_HZ configPIT_CLOCK_HZ\r
+ #define TRC_HWTC_DIVISOR 1\r
+ #define TRC_IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant\r
+\r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_APPLICATION_DEFINED)\r
+\r
+ #if !( defined (TRC_HWTC_TYPE) && defined (TRC_HWTC_COUNT) && defined (TRC_HWTC_PERIOD) && defined (TRC_HWTC_FREQ_HZ) && defined (TRC_IRQ_PRIORITY_ORDER) )\r
+ #error "The hardware port is not completely defined!"\r
+ #endif\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING\r
- #define HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )\r
- #define HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)\r
- #define HWTC_DIVISOR 16\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
-\r
-#elif (SELECTED_PORT == PORT_ARM_CORTEX_A9)\r
-\r
- /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
-\r
- #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00\r
- #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8\r
-\r
- #define CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(0xF8F00600 + 0))\r
- #define CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(0xF8F00600 + 4))\r
- #define CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(0xF8F00600 + 8))\r
-\r
- #define CA9_MPCORE_PRIVCTR_PRESCALER (((CA9_MPCORE_PRIVCTR_CONTROL_REG & CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)\r
+#elif (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)\r
\r
+ #error "TRC_CFG_HARDWARE_PORT had unsupported value!"\r
+ #define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET\r
\r
- #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING\r
- #define HWTC_COUNT CA9_MPCORE_PRIVCTR_COUNTER_REG\r
- #define HWTC_PERIOD ((CA9_MPCORE_PRIVCTR_PERIOD_REG * CA9_MPCORE_PRIVCTR_PRESCALER) + 1)\r
+#endif\r
\r
- //NOTE: The private timer ticks with a very high frequency (half the core-clock usually),\r
- //but offers the possibility to apply a prescaler. Depending on the prescaler you set the\r
- //HWTC_DIVISOR may need to be raised. Refer to the notes at the beginning of this file\r
- //for more information.\r
- #define HWTC_DIVISOR 1\r
+#ifndef TRC_HWTC_DIVISOR\r
+ #define TRC_HWTC_DIVISOR 1\r
+#endif\r
\r
- #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant\r
+#ifndef TRC_PORT_SPECIFIC_INIT\r
+ #define TRC_PORT_SPECIFIC_INIT() \r
+#endif\r
\r
-#elif (SELECTED_PORT == PORT_APPLICATION_DEFINED)\r
+/* If Win32 port */\r
+#ifdef WIN32\r
\r
- #if !( defined (HWTC_COUNT_DIRECTION) && defined (HWTC_COUNT) && defined (HWTC_PERIOD) && defined (HWTC_DIVISOR) && defined (IRQ_PRIORITY_ORDER) )\r
- #error SELECTED_PORT is PORT_APPLICATION_DEFINED but not all of the necessary constants have been defined.\r
- #endif\r
+ #undef _WIN32_WINNT\r
+ #define _WIN32_WINNT 0x0600\r
\r
-#elif (SELECTED_PORT != PORT_NOT_SET)\r
+ /* Standard includes. */\r
+ #include <stdio.h>\r
+ #include <windows.h>\r
+ #include <direct.h>\r
\r
- #error "SELECTED_PORT had unsupported value!"\r
- #define SELECTED_PORT PORT_NOT_SET\r
+ /***************************************************************************\r
+ * The Win32 port by default saves the trace to file and then kills the\r
+ * program when the recorder is stopped, to facilitate quick, simple tests\r
+ * of the recorder.\r
+ ***************************************************************************/\r
+ #define WIN32_PORT_SAVE_WHEN_STOPPED 1\r
+ #define WIN32_PORT_EXIT_WHEN_STOPPED 1\r
\r
#endif\r
\r
-#if (SELECTED_PORT != PORT_NOT_SET)\r
-\r
- #ifndef HWTC_COUNT_DIRECTION\r
- #error "HWTC_COUNT_DIRECTION is not set!"\r
+#if (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)\r
+ \r
+ #ifndef TRC_HWTC_TYPE\r
+ #error "TRC_HWTC_TYPE is not set!"\r
#endif\r
\r
- #ifndef HWTC_COUNT\r
- #error "HWTC_COUNT is not set!"\r
+ #ifndef TRC_HWTC_COUNT\r
+ #error "TRC_HWTC_COUNT is not set!"\r
#endif\r
\r
- #ifndef HWTC_PERIOD\r
- #error "HWTC_PERIOD is not set!"\r
+ #ifndef TRC_HWTC_PERIOD\r
+ #error "TRC_HWTC_PERIOD is not set!"\r
#endif\r
\r
- #ifndef HWTC_DIVISOR\r
- #error "HWTC_DIVISOR is not set!"\r
+ #ifndef TRC_HWTC_DIVISOR\r
+ #error "TRC_HWTC_DIVISOR is not set!"\r
#endif\r
\r
- #ifndef IRQ_PRIORITY_ORDER\r
- #error "IRQ_PRIORITY_ORDER is not set!"\r
- #elif (IRQ_PRIORITY_ORDER != 0) && (IRQ_PRIORITY_ORDER != 1)\r
- #error "IRQ_PRIORITY_ORDER has bad value!"\r
+ #ifndef TRC_IRQ_PRIORITY_ORDER\r
+ #error "TRC_IRQ_PRIORITY_ORDER is not set!"\r
+ #elif (TRC_IRQ_PRIORITY_ORDER != 0) && (TRC_IRQ_PRIORITY_ORDER != 1)\r
+ #error "TRC_IRQ_PRIORITY_ORDER has bad value!"\r
#endif\r
\r
- #if (HWTC_DIVISOR < 1)\r
- #error "HWTC_DIVISOR must be a non-zero positive value!"\r
+ #if (TRC_HWTC_DIVISOR < 1)\r
+ #error "TRC_HWTC_DIVISOR must be a non-zero positive value!"\r
#endif\r
-\r
+ \r
+ #ifndef TRC_HWTC_FREQ_HZ \r
+ #error "TRC_HWTC_FREQ_HZ not defined!"\r
+ #endif\r
+ \r
#endif\r
-/*******************************************************************************\r
- * vTraceConsoleMessage\r
- *\r
- * A wrapper for your system-specific console "printf" console output function.\r
- * This needs to be correctly defined to see status reports from the trace\r
- * status monitor task (this is defined in trcUser.c).\r
- ******************************************************************************/\r
-#define vTraceConsoleMessage(x)\r
-\r
-/*******************************************************************************\r
- * vTracePortGetTimeStamp\r
- *\r
- * Returns the current time based on the HWTC macros which provide a hardware\r
- * isolation layer towards the hardware timer/counter.\r
- *\r
- * The HWTC macros and vTracePortGetTimeStamp is the main porting issue\r
- * or the trace recorder library. Typically you should not need to change\r
- * the code of vTracePortGetTimeStamp if using the HWTC macros.\r
- *\r
- ******************************************************************************/\r
-void vTracePortGetTimeStamp(uint32_t *puiTimestamp);\r
\r
-#endif\r
+#endif /*TRC_SNAPSHOT_HARDWARE_PORT_H*/\r
projects / freertos / blobdiff