Update trace recorder code.

[freertos] / FreeRTOS-Plus / Source / FreeRTOS-Plus-Trace / Include / trcHardwarePort.h

diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcHardwarePort.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcHardwarePort.h
index 4be605eaa4237eda048765d785d61a9b7483309c..da31e9364bce489b715ec2b46499ba4e8f97e74d 100644 (file)
--- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcHardwarePort.h
+++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcHardwarePort.h
@@ -1,5 +1,5 @@
 /*******************************************************************************\r
- * Trace Recorder Library for Tracealyzer v3.1.2\r
+ * Trace Recorder Library for Tracealyzer v4.1.1\r
  * Percepio AB, www.percepio.com\r
  *\r
  * trcHardwarePort.h\r
@@ -38,7 +38,7 @@
  *\r
  * Tabs are used for indent in this file (1 tab = 4 spaces)\r
  *\r
- * Copyright Percepio AB, 2017.\r
+ * Copyright Percepio AB, 2018.\r
  * www.percepio.com\r
  ******************************************************************************/\r
 \r
@@ -344,7 +344,22 @@
        #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)\r
        #define TRC_IRQ_PRIORITY_ORDER 0\r
 \r
+#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Altera_NiosII)\r
+\r
+    /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */\r
+    \r
+    #include "system.h"\r
+    #include "sys/alt_timestamp.h"\r
+\r
+    #define TRC_HWTC_TYPE          TRC_OS_TIMER_INCR\r
+    #define TRC_HWTC_COUNT         (uint32_t)alt_timestamp()\r
+    #define TRC_HWTC_PERIOD        0xFFFFFFFF\r
+    #define TRC_HWTC_FREQ_HZ       TIMESTAMP_TIMER_FREQ\r
+    #define TRC_HWTC_DIVISOR       1\r
+    #define TRC_IRQ_PRIORITY_ORDER 0\r
+\r
 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)\r
+       \r
        /* INPUT YOUR PERIPHERAL BASE ADDRESS HERE */\r
        #define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS  0xSOMETHING\r
        \r