cros: adds cros_ec keyboard driver

[u-boot] / README

diff --git a/README b/README
index 2dd0bc063408f1d0aae3ed1450165d783deb845b..7196fde6259f419668eb763d7edc125003731f5e 100644 (file)
--- a/README
+++ b/README
@@ -1443,6 +1443,11 @@ CBFS (Coreboot Filesystem) support
                Export function i8042_kbd_init, i8042_tstc and i8042_getc
                for cfb_console. Supports cursor blinking.
 
+               CONFIG_CROS_EC_KEYB
+               Enables a Chrome OS keyboard using the CROS_EC interface.
+               This uses CROS_EC to communicate with a second microcontroller
+               which provides key scans on request.
+
 - Video support:
                CONFIG_VIDEO
 
@@ -2520,6 +2525,11 @@ CBFS (Coreboot Filesystem) support
                Define this option to include a destructive SPI flash
                test ('sf test').
 
+               CONFIG_SPI_FLASH_BAR            Ban/Extended Addr Reg
+
+               Define this option to use the Bank addr/Extended addr
+               support on SPI flashes which has size > 16Mbytes.
+
 - SystemACE Support:
                CONFIG_SYSTEMACE
 
@@ -3033,6 +3043,14 @@ FIT uImage format:
                CONFIG_SPL_LIBGENERIC_SUPPORT
                Support for lib/libgeneric.o in SPL binary
 
+               CONFIG_SPL_ENV_SUPPORT
+               Support for the environment operating in SPL binary
+
+               CONFIG_SPL_NET_SUPPORT
+               Support for the net/libnet.o in SPL binary.
+               It conflicts with SPL env from storage medium specified by
+               CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
                CONFIG_SPL_PAD_TO
                Image offset to which the SPL should be padded before appending
                the SPL payload. By default, this is defined as
@@ -3975,6 +3993,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_SRIO2:
                Board has SRIO 2 port available
 
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+               Board can support master function for Boot from SRIO and PCIE
+
 - CONFIG_SYS_SRIOn_MEM_VIRT:
                Virtual Address of SRIO port 'n' memory region
 
@@ -4085,6 +4106,11 @@ Low Level (hardware related) configuration options:
                that is executed before the actual U-Boot. E.g. when
                compiling a NAND SPL.
 
+- CONFIG_SYS_MPC85XX_NO_RESETVEC
+               Only for 85xx systems. If this variable is specified, the section
+               .resetvec is not kept and the section .bootpg is placed in the
+               previous 4k of the .text section.
+
 - CONFIG_ARCH_MAP_SYSMEM
                Generally U-Boot (and in particular the md command) uses
                effective address. It is therefore not necessary to regard