kernel configuration options. The intention is to make it easier to
build a config tool - later.
+- ARM Platform Bus Type(CCI):
+ CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+ provides full cache coherency between two clusters of multi-core
+ CPUs and I/O coherency for devices and I/O masters
+
+ CONFIG_SYS_FSL_HAS_CCI400
+
+ Defined For SoC that has cache coherent interconnect
+ CCN-400
+
+ CONFIG_SYS_FSL_HAS_CCN504
+
+ Defined for SoC that has cache coherent interconnect CCN-504
The following options need to be configured:
binary in its image. This device tree file should be in the
board directory and called <soc>-<board>.dts. The binary file
is then picked up in board_init_f() and made available through
- the global data structure as gd->blob.
+ the global data structure as gd->fdt_blob.
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
control registers. This behavior won't affect the
correctnessof 10/100 link speed update.
- CONFIG_SMC911X
- Support for SMSC's LAN911x and LAN921x chips
-
- CONFIG_SMC911X_BASE
- Define this to hold the physical address
- of the device (I/O space)
-
- CONFIG_SMC911X_32_BIT
- Define this if data bus is 32 bits
-
- CONFIG_SMC911X_16_BIT
- Define this if data bus is 16 bits. If your processor
- automatically converts one 32 bit word to two 16 bit
- words you may also try CONFIG_SMC911X_32_BIT.
-
CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller
this is instead controlled by the value of
/config/load-environment.
-- DataFlash Support:
- CONFIG_HAS_DATAFLASH
-
- Defining this option enables DataFlash features and
- allows to read/write in Dataflash via the standard
- commands cp, md...
-
- Serial Flash support
Usage requires an initial 'sf probe' to define the serial
flash parameters, followed by read/write/erase/update