/*\r
- FreeRTOS.org V4.7.0 - Copyright (C) 2003-2007 Richard Barry.\r
-\r
- This file is part of the FreeRTOS.org distribution.\r
-\r
- FreeRTOS.org is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- FreeRTOS.org is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with FreeRTOS.org; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
- A special exception to the GPL can be applied should you wish to distribute\r
- a combined work that includes FreeRTOS.org, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section \r
- of http://www.FreeRTOS.org for full details of how and when the exception\r
- can be applied.\r
-\r
- ***************************************************************************\r
- See http://www.FreeRTOS.org for documentation, latest information, license \r
- and contact details. Please ensure to read the configuration and relevant \r
- port sections of the online documentation.\r
-\r
- Also see http://www.SafeRTOS.com a version that has been certified for use\r
- in safety critical systems, plus commercial licensing, development and\r
- support options.\r
- ***************************************************************************\r
+ FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS books - available as PDF or paperback *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
*/\r
\r
-/*\r
- Changes between V4.0.0 and V4.0.1\r
-\r
- + Reduced the code used to setup the initial stack frame.\r
- + The kernel no longer has to install or handle the fault interrupt.\r
- \r
- Change from V4.4.0:\r
-\r
- + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the\r
- interrupt priority used by the kernel.\r
-*/\r
-\r
-\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the ARM CM3 port.\r
*----------------------------------------------------------*/\r
#include "FreeRTOS.h"\r
#include "task.h"\r
\r
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is \r
-defined. The value should also ensure backward compatibility. \r
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
+defined. The value should also ensure backward compatibility.\r
FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
#ifndef configKERNEL_INTERRUPT_PRIORITY\r
#define configKERNEL_INTERRUPT_PRIORITY 255\r
#endif\r
\r
/* Constants required to manipulate the NVIC. */\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 )\r
-#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 )\r
+#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 )\r
#define portNVIC_SYSTICK_CLK 0x00000004\r
#define portNVIC_SYSTICK_INT 0x00000002\r
#define portNVIC_SYSTICK_ENABLE 0x00000001\r
#define portNVIC_PENDSVSET 0x10000000\r
-#define portNVIC_PENDSV_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
-#define portNVIC_SYSTICK_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
+#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
+#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
\r
/* The priority used by the kernel is assigned to a variable to make access\r
from inline assembler easier. */\r
-const unsigned portLONG ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
+const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
\r
/* Each task maintains its own interrupt status in the critical nesting\r
variable. */\r
-unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
\r
-/* \r
+/*\r
* Setup the timer to generate the tick interrupts.\r
*/\r
static void prvSetupTimerInterrupt( void );\r
* Exception handlers.\r
*/\r
void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
-void xPortSysTickHandler( void ) __attribute__ (( naked ));\r
+void xPortSysTickHandler( void );\r
+void vPortSVCHandler( void ) __attribute__ (( naked ));\r
\r
/*\r
- * Set the MSP/PSP to a known value.\r
+ * Start first task is a separate function so it can be tested in isolation.\r
*/\r
-void prvSetMSP( unsigned long ulValue ) __attribute__ (( naked ));\r
-void prvSetPSP( unsigned long ulValue ) __attribute__ (( naked )); \r
+void vPortStartFirstTask( void ) __attribute__ (( naked ));\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
{\r
/* Simulate the stack frame as it would be created by a context switch\r
interrupt. */\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
*pxTopOfStack = 0; /* LR */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
- *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
\r
return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void prvSetPSP( unsigned long ulValue )\r
+void vPortSVCHandler( void )\r
{\r
- asm volatile( "msr psp, r0" );\r
- asm volatile( "bx lr" );\r
+ __asm volatile (\r
+ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */\r
+ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
+ " msr psp, r0 \n" /* Restore the task stack pointer. */\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " orr r14, #0xd \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void prvSetMSP( unsigned long ulValue )\r
+void vPortStartFirstTask( void )\r
{\r
- asm volatile( "msr msp, r0" );\r
- asm volatile( "bx lr" );\r
+ __asm volatile(\r
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n"\r
+ " ldr r0, [r0] \n"\r
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
+ " cpsie i \n"\r
+ " svc 0 \n" /* System call to start first task. */\r
+ " nop \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
portBASE_TYPE xPortStartScheduler( void )\r
{\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
here already. */\r
prvSetupTimerInterrupt();\r
- \r
- /* Start the first task. */\r
- prvSetPSP( 0 );\r
- prvSetMSP( *((unsigned portLONG *) 0 ) );\r
- *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
\r
- /* Enable interrupts */\r
- portENABLE_INTERRUPTS();\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vPortStartFirstTask();\r
\r
/* Should not get here! */\r
return 0;\r
void vPortYieldFromISR( void )\r
{\r
/* Set a PendSV to request a context switch. */\r
- *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
-\r
- /* This function is also called in response to a Yield(), so we want\r
- the yield to occur immediately. */\r
- portENABLE_INTERRUPTS();\r
+ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
void xPortPendSVHandler( void )\r
{\r
- /* Start first task if the stack has not yet been setup. */\r
+ /* This is a naked function. */\r
+\r
__asm volatile\r
- ( \r
- " mrs r0, psp \n"\r
- " cbz r0, no_save \n"\r
- " \n" /* Save the context into the TCB. */ \r
- " stmdb r0!, {r4-r11} \n"\r
- " sub r0, #0x04 \n"\r
- " ldr r1, uxCriticalNestingConst \n"\r
- " ldr r2, pxCurrentTCBConst \n"\r
- " ldr r1, [r1] \n"\r
- " ldr r2, [r2] \n"\r
- " str r1, [r0] \n" \r
- " str r0, [r2] \n"\r
- " \n"\r
- "no_save:\n" \r
- " push {r14} \n"\r
- " bl vPortSwitchContext \n"\r
- " pop {r14} \n"\r
- " \n" /* Restore the context. */ \r
- " ldr r1, pxCurrentTCBConst \n"\r
- " ldr r1, [r1] \n"\r
- " ldr r0, [r1] \n"\r
- " ldmia r0!, {r1, r4-r11} \n"\r
- " ldr r2, uxCriticalNestingConst \n"\r
- " str r1, [r2] \n"\r
- " msr psp, r0 \n"\r
- " orr r14, #0xd \n"\r
- " \n" /* Exit with interrupts in the state required by the task. */ \r
- " cbnz r1, sv_disable_interrupts \n"\r
- " bx r14 \n"\r
- " \n"\r
- "sv_disable_interrupts: \n"\r
- " ldr r1, =ulKernelPriority \n"\r
- " ldr r1, [r1] \n"\r
- " msr basepri, r1 \n"\r
- " bx r14 \n"\r
- " \n"\r
- " .align 2 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "uxCriticalNestingConst: .word uxCriticalNesting \n"\r
+ (\r
+ " mrs r0, psp \n"\r
+ " \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
+ " ldr r2, [r3] \n"\r
+ " \n"\r
+ " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */\r
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */\r
+ " \n"\r
+ " stmdb sp!, {r3, r14} \n"\r
+ " mov r0, %0 \n"\r
+ " msr basepri, r0 \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " ldmia sp!, {r3, r14} \n"\r
+ " \n" /* Restore the context, including the critical nesting count. */\r
+ " ldr r1, [r3] \n"\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */\r
+ " msr psp, r0 \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
void xPortSysTickHandler( void )\r
{\r
- extern void vTaskIncrementTick( void );\r
- extern void vPortYieldFromISR( void );\r
-\r
- /* Call the scheduler tick function. */\r
- __asm volatile\r
- ( \r
- " push {r14} \n"\r
- " bl vPortIncrementTick \n"\r
- " pop {r14}" \r
- );\r
+unsigned long ulDummy;\r
\r
/* If using preemption, also force a context switch. */\r
#if configUSE_PREEMPTION == 1\r
- __asm volatile\r
- ( \r
- " push {r14} \n"\r
- " bl vPortYieldFromISR \n"\r
- " pop {r14}" \r
- );\r
+ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
#endif\r
\r
- /* Exit with interrupts in the correct state. */\r
- __asm volatile\r
- (\r
- " ldr r2, uxCriticalNestingConst2 \n" \r
- " ldr r2, [r2] \n"\r
- " cbnz r2, tick_disable_interrupts \n"\r
- " bx r14" \r
- );\r
-\r
- __asm volatile\r
- (\r
- "tick_disable_interrupts: \n"\r
- " ldr r1, =ulKernelPriority \n"\r
- " ldr r1, [r1] \n"\r
- " msr basepri, r1 \n"\r
- " bx r14 \n"\r
- " \n"\r
- " .align 2 \n"\r
- "uxCriticalNestingConst2: .word uxCriticalNesting"\r
- );\r
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ vTaskIncrementTick();\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void prvSetupTimerInterrupt( void )\r
{\r
/* Configure SysTick to interrupt at the requested rate. */\r
- *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+ *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSwitchContext( void )\r
-{\r
- vPortSetInterruptMask();\r
- vTaskSwitchContext();\r
- vPortClearInterruptMask();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vPortIncrementTick( void )\r
-{\r
- vPortSetInterruptMask();\r
- vTaskIncrementTick();\r
- vPortClearInterruptMask();\r
-}\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
projects / freertos / blobdiff