x86: cherryhill: Fix DTC warning

[u-boot] / arch / x86 / dts / galileo.dts

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index a2f5a1f223427508c447225df87bdce965b91b4a..3454abdd33cd5f997deb614ac50055119a21d931 100644 (file)
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /dts-v1/;
@@ -18,7 +17,7 @@
        compatible = "intel,galileo", "intel,quark";
 
        aliases {
-               spi0 = "/spi";
+               spi0 = &spi;
        };
 
        config {
@@ -29,6 +28,18 @@
                stdout-path = &pciuart0;
        };
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "cpu-x86";
+                       reg = <0>;
+                       intel,apic-id = <0>;
+               };
+       };
+
        tsc-timer {
                clock-frequency = <400000000>;
        };
@@ -82,10 +93,13 @@
                pch@1f,0 {
                        reg = <0x0000f800 0 0 0 0>;
                        compatible = "intel,pch7";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
 
                        irq-router {
-                               compatible = "intel,quark-irq-router";
+                               compatible = "intel,irq-router";
                                intel,pirq-config = "pci";
+                               intel,actl-addr = <0x58>;
                                intel,pirq-link = <0x60 8>;
                                intel,pirq-mask = <0xdef8>;
                                intel,pirq-routing = <
@@ -115,10 +129,10 @@
                                >;
                        };
 
-                       spi {
+                       spi: spi {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "intel,ich-spi";
+                               compatible = "intel,ich7-spi";
                                spi-flash@0 {
                                        #size-cells = <1>;
                                        #address-cells = <1>;
@@ -132,21 +146,21 @@
                                        };
                                };
                        };
-               };
-       };
 
-       gpioa {
-               compatible = "intel,ich6-gpio";
-               u-boot,dm-pre-reloc;
-               reg = <0 0x20>;
-               bank-name = "A";
-       };
+                       gpioa {
+                               compatible = "intel,ich6-gpio";
+                               u-boot,dm-pre-reloc;
+                               reg = <0 0x20>;
+                               bank-name = "A";
+                       };
 
-       gpiob {
-               compatible = "intel,ich6-gpio";
-               u-boot,dm-pre-reloc;
-               reg = <0x20 0x20>;
-               bank-name = "B";
+                       gpiob {
+                               compatible = "intel,ich6-gpio";
+                               u-boot,dm-pre-reloc;
+                               reg = <0x20 0x20>;
+                               bank-name = "B";
+                       };
+               };
        };
 
 };