* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
#if 0
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(0);
#endif
/* set SDRAM CS1 size according to the amount of RAM found */
/* adjust mapping */
*(vu_long *) MPC5XXX_BOOTCS_START =
*(vu_long *) MPC5XXX_CS0_START =
- START_REG(CFG_BOOTCS_START | size);
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
*(vu_long *) MPC5XXX_BOOTCS_STOP =
*(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CFG_BOOTCS_START | size, size);
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
}
}
extern void pci_mpc5xxx_init(struct pci_controller *);
-void pci_init_board(void
- ) {
+void pci_init_board(void) {
pci_mpc5xxx_init(&hose);
}
#endif
-#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void init_ide_reset(void)
{
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
-#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+#endif
#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
}
}
-int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
unsigned int addr;
unsigned int size;
}
U_BOOT_CMD(writepci, 3, 1, do_writepci,
- "writepci- Write some data to pcibus\n",
- "<addr> <size>\n" " - Write some data to pcibus.\n");
+ "Write some data to pcibus",
+ "<addr> <size>\n"
+ ""
+);