+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2008 Semihalf
*
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef USE_HOSTCC
#include <mapmem.h>
#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
-#include <libfdt.h>
+#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fpga.h>
#include <xilinx.h>
{ IH_ARCH_ARC, "arc", "ARC", },
{ IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ IH_ARCH_XTENSA, "xtensa", "Xtensa", },
+ { IH_ARCH_RISCV, "riscv", "RISC-V", },
{ -1, "", "", },
};
{ IH_OS_OSE, "ose", "Enea OSE", },
{ IH_OS_PLAN9, "plan9", "Plan 9", },
{ IH_OS_RTEMS, "rtems", "RTEMS", },
+ { IH_OS_TEE, "tee", "Trusted Execution Environment" },
{ IH_OS_U_BOOT, "u-boot", "U-Boot", },
{ IH_OS_VXWORKS, "vxworks", "VxWorks", },
#if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
{ IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",},
{ IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", },
{ IH_TYPE_SCRIPT, "script", "Script", },
- { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",},
+ { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SoCFPGA CV/AV preloader",},
+ { IH_TYPE_SOCFPGAIMAGE_V1, "socfpgaimage_v1", "Altera SoCFPGA A10 preloader",},
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
{ IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",},
{ IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",},
{ IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",},
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
{ IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",},
+ { IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
{ -1, "", "", },
};
* AMP boot scenarios in which we might not be
* HW cache coherent
*/
- flush_cache((unsigned long)*initrd_start, rd_len);
+ flush_cache((unsigned long)*initrd_start,
+ ALIGN(rd_len, ARCH_DMA_MINALIGN));
#endif
puts("OK\n");
}