+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Intel Corporation <www.intel.com>
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#include <asm/io.h>
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x1000000
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_fpga_manager *fpga_manager_base =
(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
- /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
- * timeout at 1000ms
+ /*
+ * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+ * de-asserted, timeout at 1000ms
*/
- return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
- mask,
- false, FPGA_TIMEOUT_MSEC, false);
+ return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
+ true, FPGA_TIMEOUT_MSEC, false);
}
static int wait_for_f2s_nstatus_pin(unsigned long value)