mmc: matsushita-common: Wait for command completion

[u-boot] / drivers / mmc / matsushita-common.h

diff --git a/drivers/mmc/matsushita-common.h b/drivers/mmc/matsushita-common.h
index e517a2d56b13c07fad969bfc4aa49f9ae9b55b43..34631cb43ea2e8eb5d4a0499e9c91389c5a3dc84 100644 (file)
--- a/drivers/mmc/matsushita-common.h
+++ b/drivers/mmc/matsushita-common.h
@@ -38,6 +38,7 @@
 #define MATSU_SD_INFO2                 0x03c   /* IRQ status 2 */
 #define   MATSU_SD_INFO2_ERR_ILA       BIT(15) /* illegal access err */
 #define   MATSU_SD_INFO2_CBSY          BIT(14) /* command busy */
+#define   MATSU_SD_INFO2_SCLKDIVEN     BIT(13) /* command setting reg ena */
 #define   MATSU_SD_INFO2_BWE           BIT(9)  /* write buffer ready */
 #define   MATSU_SD_INFO2_BRE           BIT(8)  /* read buffer ready */
 #define   MATSU_SD_INFO2_DAT0          BIT(7)  /* SDDAT0 */
@@ -63,6 +64,7 @@
 #define   MATSU_SD_CLKCTL_DIV4         BIT(0)  /* SDCLK = CLK / 4 */
 #define   MATSU_SD_CLKCTL_DIV2         0       /* SDCLK = CLK / 2 */
 #define   MATSU_SD_CLKCTL_DIV1         BIT(10) /* SDCLK = CLK */
+#define   MATSU_SD_CLKCTL_RCAR_DIV1    0xff    /* SDCLK = CLK (RCar ver.) */
 #define   MATSU_SD_CLKCTL_OFFEN                BIT(9)  /* stop SDCLK when unused */
 #define   MATSU_SD_CLKCTL_SCLKEN       BIT(8)  /* SDCLK output enable */
 #define MATSU_SD_SIZE                  0x04c   /* block size */
@@ -95,8 +97,8 @@
 #define   MATSU_SD_DMA_RST_RD          BIT(9)
 #define   MATSU_SD_DMA_RST_WR          BIT(8)
 #define MATSU_SD_DMA_INFO1             0x420
-#define   MATSU_SD_DMA_INFO1_END_RD2   BIT(20) /* DMA from device is complete*/
-#define   MATSU_SD_DMA_INFO1_END_RD    BIT(17) /* Don't use!  Hardware bug */
+#define   MATSU_SD_DMA_INFO1_END_RD2   BIT(20) /* DMA from device is complete (uniphier) */
+#define   MATSU_SD_DMA_INFO1_END_RD    BIT(17) /* DMA from device is complete (renesas) */
 #define   MATSU_SD_DMA_INFO1_END_WR    BIT(16) /* DMA to device is complete */
 #define MATSU_SD_DMA_INFO1_MASK                0x424
 #define MATSU_SD_DMA_INFO2             0x428
@@ -123,6 +125,15 @@ struct matsu_sd_priv {
 #define MATSU_SD_CAP_DMA_INTERNAL      BIT(1)  /* have internal DMA engine */
 #define MATSU_SD_CAP_DIV1024           BIT(2)  /* divisor 1024 is available */
 #define MATSU_SD_CAP_64BIT             BIT(3)  /* Controller is 64bit */
+#define MATSU_SD_CAP_16BIT             BIT(4)  /* Controller is 16bit */
+#define MATSU_SD_CAP_RCAR_GEN2         BIT(5)  /* Renesas RCar version of IP */
+#define MATSU_SD_CAP_RCAR_GEN3         BIT(6)  /* Renesas RCar version of IP */
+#define MATSU_SD_CAP_RCAR_UHS          BIT(7)  /* Renesas RCar UHS/SDR modes */
+#define MATSU_SD_CAP_RCAR              \
+       (MATSU_SD_CAP_RCAR_GEN2 | MATSU_SD_CAP_RCAR_GEN3)
+#ifdef CONFIG_DM_REGULATOR
+       struct udevice *vqmmc_dev;
+#endif
 };
 
 int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
@@ -131,6 +142,10 @@ int matsu_sd_set_ios(struct udevice *dev);
 int matsu_sd_get_cd(struct udevice *dev);
 
 int matsu_sd_bind(struct udevice *dev);
-int matsu_sd_probe(struct udevice *dev);
+int matsu_sd_probe(struct udevice *dev, u32 quirks);
+
+u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg);
+void matsu_sd_writel(struct matsu_sd_priv *priv,
+                    u32 val, unsigned int reg);
 
 #endif /* __MATSUSHITA_COMMON_H__ */