+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DRIVERS_MACB_H__
#define __DRIVERS_MACB_H__
#define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008
#define GEM_UR 0x000c
+#define MACB_DMACFG 0x0010
#define MACB_TSR 0x0014
#define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c
#define MACB_WOL 0x00c4
#define MACB_MID 0x00fc
+/* GEM specific register offsets */
+#define GEM_DCFG1 0x0280
+#define GEM_DCFG6 0x0294
+
+#define MACB_MAX_QUEUES 8
+
+/* GEM specific multi queues register offset */
+/* hw_q can be 0~7 */
+#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
+
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
#define MACB_IDNUM_SIZE 16
/* Bitfields in DCFG1 */
+#define GEM_DBWDEF_OFFSET 25
+#define GEM_DBWDEF_SIZE 3
+
+/* constants for data bus width */
+#define GEM_DBW32 0
+#define GEM_DBW64 1
+#define GEM_DBW128 2
+
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
readl((port)->regs + GEM_##reg)
#define gem_writel(port, reg, value) \
writel((value), (port)->regs + GEM_##reg)
+#define gem_writel_queue_TBQP(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_TBQP(queue_num))
#endif /* __DRIVERS_MACB_H__ */