+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
u64 size)
{
u32 sz = (__ilog2_u64(size) - 1);
- u32 flag = PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ u32 flag = 0;
+#else
+ u32 flag = PIWAR_LOCAL;
+#endif
+
+ flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
out_be32(&pi->pitar, r->phys_start >> 12);
out_be32(&pi->piwbar, r->bus_start >> 12);
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
- char *s = getenv("bootmaster");
+ char *s = env_get("bootmaster");
char pcie[6];
sprintf(pcie, "PCIE%d", pci_info->pci_num);
ltssm = (in_be32(&pci->pex_csr0)
& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
enabled = (ltssm == 0x11) ? 1 : 0;
+#ifdef CONFIG_FSL_PCIE_RESET
+ int i;
+ /* assert PCIe reset */
+ setbits_be32(&pci->pdb_stat, 0x08000000);
+ (void) in_be32(&pci->pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(&pci->pdb_stat, 0x08000000);
+ asm("sync;isync");
+ for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ <ssm);
+ udelay(1000);
+ }
+#endif
} else {
/* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
/* enabled = ltssm >= PCI_LTSSM_L0; */
}
#endif
if (!enabled) {
- /* Let the user know there's no PCIe link */
- printf("no link, regs @ 0x%lx\n", pci_info->regs);
+ /* Let the user know there's no PCIe link for root
+ * complex. for endpoint, the link may not setup, so
+ * print undetermined.
+ */
+ if (fsl_is_pci_agent(hose))
+ printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
+ else
+ printf("no link, regs @ 0x%lx\n", pci_info->regs);
hose->last_busno = hose->first_busno;
return;
}
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+ /* The Read-Only Write Enable bit defaults to 1 instead of 0.
+ * Set to 0 to protect the read-only registers.
+ */
+ clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
+#endif
+
/* Use generic setup_device to initialize standard pci regs,
* but do not allocate any windows since any BAR found (such
* as PCSRBAR) is not in this cpu's memory space.
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
} else {
/* boot from PCIE --master releases slave's core 0 */
- char *s = getenv("bootmaster");
+ char *s = env_get("bootmaster");
char pcie[6];
sprintf(pcie, "PCIE%d", pci_info->pci_num);
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
if (pcie_cap != 0x0) {
+ ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
+ u32 block_rev = in_be32(&pci->block_rev1);
/* PCIe - set CFG_READY bit of Configuration Ready Register */
- pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+ if (block_rev >= PEX_IP_BLK_REV_3_0)
+ setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
+ else
+ pci_hose_write_config_byte(hose, dev,
+ FSL_PCIE_CFG_RDY, 0x1);
} else {
/* PCI - clear ACL bit of PBFR */
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
+#include <linux/libfdt.h>
#include <fdt_support.h>
void ft_fsl_pci_setup(void *blob, const char *pci_compat,