+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2014 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
return sub_bus;
}
+int pci_generic_mmap_write_config(
+ struct udevice *bus,
+ int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+ pci_dev_t bdf,
+ uint offset,
+ ulong value,
+ enum pci_size_t size)
+{
+ void *address;
+
+ if (addr_f(bus, bdf, offset, &address) < 0)
+ return 0;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(value, address);
+ return 0;
+ case PCI_SIZE_16:
+ writew(value, address);
+ return 0;
+ case PCI_SIZE_32:
+ writel(value, address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+int pci_generic_mmap_read_config(
+ struct udevice *bus,
+ int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+ pci_dev_t bdf,
+ uint offset,
+ ulong *valuep,
+ enum pci_size_t size)
+{
+ void *address;
+
+ if (addr_f(bus, bdf, offset, &address) < 0) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = readb(address);
+ return 0;
+ case PCI_SIZE_16:
+ *valuep = readw(address);
+ return 0;
+ case PCI_SIZE_32:
+ *valuep = readl(address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
int dm_pci_hose_probe_bus(struct udevice *bus)
{
int sub_bus;
return ret;
}
-static int decode_regions(struct pci_controller *hose, ofnode parent_node,
- ofnode node)
+static void decode_regions(struct pci_controller *hose, ofnode parent_node,
+ ofnode node)
{
int pci_addr_cells, addr_cells, size_cells;
- phys_addr_t base = 0, size;
int cells_per_record;
const u32 *prop;
int len;
int i;
prop = ofnode_get_property(node, "ranges", &len);
- if (!prop)
- return -EINVAL;
+ if (!prop) {
+ debug("%s: Cannot decode regions\n", __func__);
+ return;
+ }
+
pci_addr_cells = ofnode_read_simple_addr_cells(node);
addr_cells = ofnode_read_simple_addr_cells(parent_node);
size_cells = ofnode_read_simple_size_cells(node);
} else {
continue;
}
+
+ if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+ type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
+ debug(" - beyond the 32-bit boundary, ignoring\n");
+ continue;
+ }
+
pos = -1;
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == type)
}
/* Add a region for our local memory */
+#ifdef CONFIG_NR_DRAM_BANKS
+ bd_t *bd = gd->bd;
+
+ if (!bd)
+ return;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ pci_set_region(hose->regions + hose->region_count++,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ }
+ }
+#else
+ phys_addr_t base = 0, size;
+
size = gd->ram_size;
#ifdef CONFIG_SYS_SDRAM_BASE
base = CONFIG_SYS_SDRAM_BASE;
#endif
if (gd->pci_ram_top && gd->pci_ram_top < base + size)
size = gd->pci_ram_top - base;
- pci_set_region(hose->regions + hose->region_count++, base, base,
- size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ if (size)
+ pci_set_region(hose->regions + hose->region_count++, base,
+ base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+#endif
- return 0;
+ return;
}
static int pci_uclass_pre_probe(struct udevice *bus)
{
struct pci_controller *hose;
- int ret;
debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
bus->parent->name);
/* For bridges, use the top-level PCI controller */
if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus;
- ret = decode_regions(hose, dev_ofnode(bus->parent),
- dev_ofnode(bus));
- if (ret) {
- debug("%s: Cannot decode regions\n", __func__);
- return ret;
- }
+ decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
} else {
struct pci_controller *parent_hose;
struct pci_region *res;
int i;
+ if (hose->region_count == 0) {
+ *pa = bus_addr;
+ return 0;
+ }
+
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
ctlr = pci_get_controller(dev);
hose = dev_get_uclass_priv(ctlr);
+ if (hose->region_count == 0) {
+ *ba = phys_addr;
+ return 0;
+ }
+
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];