/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
+#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
+#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
+#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
/*
* Initial bus setup
*/
-static int imx6_pcie_assert_core_reset(void)
+static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* Power up PCIe PHY */
setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
#else
+ /*
+ * If the bootloader already enabled the link we need some special
+ * handling to get the core back into a state where it is safe to
+ * touch it for configuration. As there is no dedicated reset signal
+ * wired up for MX6QDL, we need to manually force LTSSM into "detect"
+ * state before completely disabling LTSSM, which is a prerequisite
+ * for core configuration.
+ *
+ * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
+ * indication that the bootloader activated the link.
+ */
+ if (is_mx6dq() && prepare_for_boot) {
+ u32 val, gpr1, gpr12;
+
+ gpr1 = readl(&iomuxc_regs->gpr[1]);
+ gpr12 = readl(&iomuxc_regs->gpr[12]);
+ if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
+ (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
+ val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+ val |= PCIE_PL_PFLR_FORCE_LINK;
+
+ imx_pcie_fix_dabt_handler(true);
+ writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
+ imx_pcie_fix_dabt_handler(false);
+
+ gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
+ writel(val, &iomuxc_regs->gpr[12]);
+ }
+ }
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
#endif
__weak int imx6_pcie_toggle_power(void)
{
#ifdef CONFIG_PCIE_IMX_POWER_GPIO
+ gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
mdelay(20);
+ gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
#endif
return 0;
}
* state due to being previously used in U-Boot.
*/
#ifdef CONFIG_PCIE_IMX_PERST_GPIO
+ gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
mdelay(20);
+ gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
#else
puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
#endif
uint32_t tmp;
int count = 0;
- imx6_pcie_assert_core_reset();
+ imx6_pcie_assert_core_reset(false);
imx6_pcie_init_phy();
imx6_pcie_deassert_core_reset();
imx_pcie_regions_setup();
+ /*
+ * By default, the subordinate is set equally to the secondary
+ * bus (0x01) when the RC boots.
+ * This means that theoretically, only bus 1 is reachable from the RC.
+ * Force the PCIe RC subordinate to 0xff, otherwise no downstream
+ * devices will be detected if the enumeration is applied strictly.
+ */
+ tmp = readl(MX6_DBI_ADDR + 0x18);
+ tmp |= (0xff << 16);
+ writel(tmp, MX6_DBI_ADDR + 0x18);
+
/*
* FIXME: Force the PCIe RC to Gen1 operation
* The RC must be forced into Gen1 mode before bringing the link
while (!imx6_pcie_link_up()) {
udelay(10);
count++;
- if (count >= 2000) {
+ if (count >= 4000) {
#ifdef CONFIG_PCI_SCAN_SHOW
puts("PCI: pcie phy link never came up\n");
#endif
}
}
+void imx_pcie_remove(void)
+{
+ imx6_pcie_assert_core_reset(true);
+}
+
/* Probe function. */
void pci_init_board(void)
{