+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2017
- * Vikas Manocha, <vikas.manocha@st.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
#include <ram.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
+#define MEM_MODE_MASK GENMASK(2, 0)
+#define SWP_FMC_OFFSET 10
+#define SWP_FMC_MASK GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
+#define NOT_FOUND 0xff
struct stm32_fmc_regs {
/* 0x0 */
u32 sdsr; /* SDRAM Status register */
};
+/*
+ * NOR/PSRAM Control register BCR1
+ * FMC controller Enable, only availabe for H7
+ */
+#define FMC_BCR1_FMCEN BIT(31)
+
/* Control register SDCR */
#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
MAX_SDRAM_BANK,
};
+enum stm32_fmc_family {
+ STM32F7_FMC,
+ STM32H7_FMC,
+};
+
struct bank_params {
struct stm32_sdram_control *sdram_control;
struct stm32_sdram_timing *sdram_timing;
struct stm32_fmc_regs *base;
u8 no_sdram_banks;
struct bank_params bank_params[MAX_SDRAM_BANK];
+ enum stm32_fmc_family family;
};
#define SDRAM_MODE_BL_SHIFT 0
u32 ref_count;
u8 i;
+ /* disable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
+
for (i = 0; i < params->no_sdram_banks; i++) {
control = params->bank_params[i].sdram_control;
timing = params->bank_params[i].sdram_timing;
| timing->txsr << FMC_SDTR_TXSR_SHIFT
| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
®s->sdtr2);
+
if (target_bank == SDRAM_BANK1)
ctb = FMC_SDCMR_BANK_1;
else
writel(ref_count << 1, ®s->sdrtr);
}
+ /* enable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ setbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
+
return 0;
}
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
struct bank_params *bank_params;
+ struct ofnode_phandle_args args;
+ u32 *syscfg_base;
+ u32 mem_remap;
+ u32 swp_fmc;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (ret) {
+ dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
+ } else {
+ syscfg_base = (u32 *)ofnode_get_addr(args.node);
+
+ mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
+ if (mem_remap != NOT_FOUND) {
+ /* set memory mapping selection */
+ clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
+ } else {
+ dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
+ }
+
+ swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
+ if (swp_fmc != NOT_FOUND) {
+ /* set fmc swapping selection */
+ clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
+ } else {
+ dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
+ }
+
+ dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
+ }
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
bank_name = (char *)ofnode_get_name(bank_node);
strsep(&bank_name, "@");
if (!bank_name) {
- error("missing sdram bank index");
+ pr_err("missing sdram bank index");
return -EINVAL;
}
(long unsigned int *)&bank_params->target_bank);
if (bank_params->target_bank >= MAX_SDRAM_BANK) {
- error("Found bank %d , but only bank 0 and 1 are supported",
+ pr_err("Found bank %d , but only bank 0 and 1 are supported",
bank_params->target_bank);
return -EINVAL;
}
sizeof(struct stm32_sdram_control));
if (!params->bank_params[bank].sdram_control) {
- error("st,sdram-control not found for %s",
+ pr_err("st,sdram-control not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
sizeof(struct stm32_sdram_timing));
if (!params->bank_params[bank].sdram_timing) {
- error("st,sdram-timing not found for %s",
+ pr_err("st,sdram-timing not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
return -EINVAL;
params->base = (struct stm32_fmc_regs *)addr;
+ params->family = dev_get_driver_data(dev);
#ifdef CONFIG_CLK
struct clk clk;
};
static const struct udevice_id stm32_fmc_ids[] = {
- { .compatible = "st,stm32-fmc" },
+ { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
+ { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
{ }
};