Merge branch 'master' of git://git.denx.de/u-boot-uniphier

[u-boot] / drivers / timer / tsc_timer.c

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 77040afafe7f93ad2993d466550e14e10d1264c2..cf869998bf9cc1da3e3d5f1a28c732996bbc8f63 100644 (file)
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2012 The Chromium OS Authors.
  *
  * TSC calibration codes are adapted from Linux kernel
  * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -22,6 +21,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static unsigned long cpu_mhz_from_cpuid(void)
+{
+       if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+               return 0;
+
+       if (cpuid_eax(0) < 0x16)
+               return 0;
+
+       return cpuid_eax(0x16);
+}
+
 /*
  * According to Intel 64 and IA-32 System Programming Guide,
  * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@@ -331,32 +341,60 @@ static int tsc_timer_get_count(struct udevice *dev, u64 *count)
        return 0;
 }
 
-static int tsc_timer_probe(struct udevice *dev)
+static void tsc_timer_ensure_setup(void)
 {
-       struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
+       if (gd->arch.tsc_base)
+               return;
        gd->arch.tsc_base = rdtsc();
 
        /*
         * If there is no clock frequency specified in the device tree,
         * calibrate it by ourselves.
         */
-       if (!uc_priv->clock_rate) {
+       if (!gd->arch.clock_rate) {
                unsigned long fast_calibrate;
 
+               fast_calibrate = cpu_mhz_from_cpuid();
+               if (fast_calibrate)
+                       goto done;
+
                fast_calibrate = cpu_mhz_from_msr();
-               if (!fast_calibrate) {
-                       fast_calibrate = quick_pit_calibrate();
-                       if (!fast_calibrate)
-                               panic("TSC frequency is ZERO");
-               }
+               if (fast_calibrate)
+                       goto done;
+
+               fast_calibrate = quick_pit_calibrate();
+               if (fast_calibrate)
+                       goto done;
 
-               uc_priv->clock_rate = fast_calibrate * 1000000;
+               panic("TSC frequency is ZERO");
+
+done:
+               gd->arch.clock_rate = fast_calibrate * 1000000;
        }
+}
+
+static int tsc_timer_probe(struct udevice *dev)
+{
+       struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+       tsc_timer_ensure_setup();
+       uc_priv->clock_rate = gd->arch.clock_rate;
 
        return 0;
 }
 
+unsigned long notrace timer_early_get_rate(void)
+{
+       tsc_timer_ensure_setup();
+
+       return gd->arch.clock_rate;
+}
+
+u64 notrace timer_early_get_count(void)
+{
+       return rdtsc() - gd->arch.tsc_base;
+}
+
 static const struct timer_ops tsc_timer_ops = {
        .get_count = tsc_timer_get_count,
 };