#define PCI_DCR 0x54 /* PCIe Device Control Register */
#define PCI_DSR 0x56 /* PCIe Device Status Register */
#define PCI_LSR 0x5e /* PCIe Link Status Register */
+#define PCI_LCR 0x5c /* PCIe Link Control Register */
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
#define PCI_LTSSM_L0 0x16 /* L0 state */
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
int current_busno;
+
+ void *priv_data;
};
extern __inline__ void pci_set_ops(struct pci_controller *hose,