module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");
+static bool ignore_resource_conflict;
+module_param(ignore_resource_conflict, bool, 0);
+MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
+
static struct platform_device *it87_pdev[2];
#define REG_2E 0x2e /* The register to read/write */
const struct attribute_group *groups[7];
enum chips type;
u32 features;
- u8 bank;
u8 peci_mask;
u8 old_peci_mask;
s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
u8 num_temp_limit; /* Number of temperature limit registers */
u8 num_temp_offset; /* Number of temperature offset registers */
+ u8 temp_src[4]; /* Up to 4 temperature source registers */
u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
}
-static void it87_set_bank(struct it87_data *data, u8 bank)
+static u8 it87_set_bank(struct it87_data *data, u8 bank)
{
- if (has_bank_sel(data) && bank != data->bank) {
+ u8 _bank = bank;
+
+ if (has_bank_sel(data)) {
u8 breg = _it87_read_value(data, IT87_REG_BANK);
- breg &= 0x1f;
- breg |= (bank << 5);
- data->bank = bank;
- _it87_write_value(data, IT87_REG_BANK, breg);
+ _bank = breg >> 5;
+ if (bank != _bank) {
+ breg &= 0x1f;
+ breg |= (bank << 5);
+ _it87_write_value(data, IT87_REG_BANK, breg);
+ }
}
+ return _bank;
}
/*
*/
static int it87_read_value(struct it87_data *data, u16 reg)
{
- it87_set_bank(data, reg >> 8);
- return _it87_read_value(data, reg & 0xff);
+ u8 bank;
+ int val;
+
+ bank = it87_set_bank(data, reg >> 8);
+ val = _it87_read_value(data, reg & 0xff);
+ it87_set_bank(data, bank);
+
+ return val;
}
/*
*/
static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
{
- it87_set_bank(data, reg >> 8);
+ u8 bank;
+
+ bank = it87_set_bank(data, reg >> 8);
_it87_write_value(data, reg & 0xff, value);
+ it87_set_bank(data, bank);
}
static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
set_temp, 5, 3);
+static const u8 temp_types_8686[NUM_TEMP][9] = {
+ { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
+ { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
+ { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
+ { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
+ { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
+ { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
+};
+
static int get_temp_type(struct it87_data *data, int index)
{
u8 reg, extra;
int type = 0;
if (has_bank_sel(data)) {
- int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
u8 src1, src2;
- src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
- src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
+ src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
switch (data->type) {
case it8686:
- switch (src1) {
- case 0:
- if (index >= 3)
- return 4;
- break;
- case 1:
- if (index == 1 || index == 2 ||
- index == 4 || index == 5)
- return 6;
- break;
- case 2:
- if (index == 2 || index == 6)
- return 5;
- break;
- default:
- break;
- }
+ if (src1 < 9)
+ type = temp_types_8686[index][src1];
break;
case it8625:
if (index < 3)
index = src1;
break;
}
+ src2 = data->temp_src[3];
switch(src1) {
case 3:
type = (src2 & BIT(index)) ? 6 : 5;
return 0;
}
}
- if (index >= 3)
- return 0;
+ if (type || index >= 3)
+ return type;
reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
if (has_newer_autopwm(data)) {
ctrl = temp_map_to_reg(data, nr,
data->pwm_temp_map[nr]);
+ ctrl &= 0x7f;
} else {
ctrl = data->pwm_duty[nr];
}
if (has_newer_autopwm(data)) {
ctrl = temp_map_to_reg(data, nr,
data->pwm_temp_map[nr]);
- if (val != 1)
+ if (val == 1)
+ ctrl &= 0x7f;
+ else
ctrl |= 0x80;
} else {
ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
}
}
+ if (has_bank_sel(data)) {
+ for (i = 0; i < 3; i++)
+ data->temp_src[i] =
+ it87_read_value(data, IT87_REG_TEMP_SRC1[i]);
+ data->temp_src[3] = it87_read_value(data, IT87_REG_TEMP_SRC2);
+ }
+
/* Start monitoring */
it87_write_value(data, IT87_REG_CONFIG,
(it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
data->peci_mask = it87_devices[sio_data->type].peci_mask;
data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
- data->bank = 0xff;
/*
* IT8705F Datasheet 0.4.1, 3h == Version G.
int err;
err = acpi_check_resource_conflict(&res);
- if (err)
- return err;
+ if (err) {
+ if (!ignore_resource_conflict)
+ return err;
+ }
pdev = platform_device_alloc(DRVNAME, address);
if (!pdev)
* the second chip may have been accessed prior to loading this driver.
*
* The problem is also reported to affect IT8795E, which is used on X299 boards
- * and has the same chip ID as IT9792E (0x8733). It also appears to affect
+ * and has the same chip ID as IT8792E (0x8733). It also appears to affect
* systems with IT8790E, which is used on some Z97X-Gaming boards as well as
* Z87X-OC.
* DMI entries for those systems will be added as they become available and