static void nand_wait(void)
{
- lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
+ fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
for (;;) {
uint32_t status = in_be32(®s->ltesr);
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
- lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
- uchar *buf = (uchar *)CFG_NAND_BASE;
+ fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+ uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
int large = in_be32(®s->bank[0].or) & OR_FCM_PGS;
int block_shift = large ? 17 : 14;
int block_size = 1 << block_shift;
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
- (uchar *)CFG_NAND_U_BOOT_DST);
+ nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
/*
* Jump to U-Boot image
*/
puts("transfering control\n");
- uboot = (void *)CFG_NAND_U_BOOT_START;
+ /*
+ * Clean d-cache and invalidate i-cache, to
+ * make sure that no stale data is executed.
+ */
+ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
}