size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
+ uint32_t addr_xor;
int retval;
- if (size == 4)
+ /* TI BE-32 Quirks mode:
+ * Writes on big-endian TMS570 behave very strangely. Observed behavior:
+ * size write address bytes written in order
+ * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
+ * 2 TAR ^ 2 (val >> 8), (val)
+ * 1 TAR ^ 3 (val)
+ * For example, if you attempt to write a single byte to address 0, the processor
+ * will actually write a byte to address 3.
+ *
+ * To make writes of size < 4 work as expected, we xor a value with the address before
+ * setting the TAP, and we set the TAP after every transfer rather then relying on
+ * address increment. */
+
+ if (size == 4) {
csw_size = CSW_32BIT;
- else if (size == 2)
+ addr_xor = 0;
+ } else if (size == 2) {
csw_size = CSW_16BIT;
- else if (size == 1)
+ addr_xor = dap->ti_be_32_quirks ? 2 : 0;
+ } else if (size == 1) {
csw_size = CSW_8BIT;
- else
+ addr_xor = dap->ti_be_32_quirks ? 3 : 0;
+ } else {
return ERROR_TARGET_UNALIGNED_ACCESS;
+ }
- retval = dap_setup_accessport_tar(dap, address);
+ if (dap->unaligned_access_bad && (address % size != 0))
+ return ERROR_TARGET_UNALIGNED_ACCESS;
+
+ retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
if (retval != ERROR_OK)
return retval;
/* How many source bytes each transfer will consume, and their location in the DRW,
* depends on the type of transfer and alignment. See ARM document IHI0031C. */
uint32_t outvalue = 0;
- switch (this_size) {
- case 4:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
- case 2:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
- case 1:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ if (dap->ti_be_32_quirks) {
+ switch (this_size) {
+ case 4:
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
+ break;
+ case 2:
+ outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
+ break;
+ case 1:
+ outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
+ break;
+ }
+ } else {
+ switch (this_size) {
+ case 4:
+ outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ case 2:
+ outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ case 1:
+ outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ }
}
nbytes -= this_size;
if (retval != ERROR_OK)
break;
- /* Rewrite TAR if it wrapped */
- if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
- retval = dap_setup_accessport_tar(dap, address);
+ /* Rewrite TAR if it wrapped or we're xoring addresses */
+ if (addrinc && (addr_xor || (address % dap->tar_autoincr_block < size && nbytes > 0))) {
+ retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
if (retval != ERROR_OK)
break;
}
uint32_t address = adr;
int retval;
+ /* TI BE-32 Quirks mode:
+ * Reads on big-endian TMS570 behave strangely differently than writes.
+ * They read from the physical address requested, but with DRW byte-reversed.
+ * For example, a byte read from address 0 will place the result in the high bytes of DRW.
+ * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
+ * so avoid them. */
+
if (size == 4)
csw_size = CSW_32BIT;
else if (size == 2)
else
return ERROR_TARGET_UNALIGNED_ACCESS;
+ if (dap->unaligned_access_bad && (adr % size != 0))
+ return ERROR_TARGET_UNALIGNED_ACCESS;
+
/* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
* over-allocation if packed transfers are going to be used, but determining the real need at
* this point would be messy. */
}
retval = dap_setup_accessport_tar(dap, address);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ free(read_buf);
return retval;
+ }
/* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
* useful bytes it contains, and their location in the word, depends on the type of transfer
this_size = 4;
}
- switch (this_size) {
- case 4:
- *buffer++ = *read_ptr >> 8 * (address++ & 3);
- *buffer++ = *read_ptr >> 8 * (address++ & 3);
- case 2:
- *buffer++ = *read_ptr >> 8 * (address++ & 3);
- case 1:
- *buffer++ = *read_ptr >> 8 * (address++ & 3);
+ if (dap->ti_be_32_quirks) {
+ switch (this_size) {
+ case 4:
+ *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ case 2:
+ *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ case 1:
+ *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ }
+ } else {
+ switch (this_size) {
+ case 4:
+ *buffer++ = *read_ptr >> 8 * (address++ & 3);
+ *buffer++ = *read_ptr >> 8 * (address++ & 3);
+ case 2:
+ *buffer++ = *read_ptr >> 8 * (address++ & 3);
+ case 1:
+ *buffer++ = *read_ptr >> 8 * (address++ & 3);
+ }
}
read_ptr++;
dap_syssec(dap);
/* check that we support packed transfers */
- uint32_t csw;
+ uint32_t csw, cfg;
retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
return retval;
+ retval = dap_queue_ap_read(dap, AP_REG_CFG, &cfg);
+ if (retval != ERROR_OK)
+ return retval;
+
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
else
dap->packed_transfers = false;
+ /* Packed transfers on TI BE-32 processors do not work correctly in
+ * many cases. */
+ if (dap->ti_be_32_quirks)
+ dap->packed_transfers = false;
+
LOG_DEBUG("MEM_AP Packed Transfers: %s",
dap->packed_transfers ? "enabled" : "disabled");
+ /* The ARM ADI spec leaves implementation-defined whether unaligned
+ * memory accesses work, only work partially, or cause a sticky error.
+ * On TI BE-32 processors, reads seem to return garbage in some bytes
+ * and unaligned writes seem to cause a sticky error.
+ * TODO: it would be nice to have a way to detect whether unaligned
+ * operations are supported on other processors. */
+ dap->unaligned_access_bad = dap->ti_be_32_quirks;
+
+ LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
+ !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
+
return ERROR_OK;
}
int retval;
uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
uint16_t entry_offset;
- int i;
- char tabs[16 + 1];
+ char tabs[7] = "";
if (depth > 16) {
command_print(cmd_ctx, "\tTables too deep");
return ERROR_FAIL;
}
- for (i = 0; i < depth; ++i)
- tabs[i] = '\t';
- tabs[i] = '\0';
+ if (depth)
+ snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
/* bit 16 of apid indicates a memory access port */
if (dbgbase & 0x02)
return retval;
c_cid3 &= 0xff;
- command_print(cmd_ctx, "\t%s\tComponent base address 0x%" PRIx32 ", "
- "start address 0x%" PRIx32, tabs, component_base,
+ command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
+ "start address 0x%" PRIx32, component_base,
/* component may take multiple 4K pages */
(uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
- command_print(cmd_ctx, "\t%s\tComponent class is 0x%x, %s",
- tabs, (c_cid1 >> 4) & 0xf,
+ command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
+ (c_cid1 >> 4) & 0xf,
/* See ARM IHI 0029B Table 3-3 */
class_description[(c_cid1 >> 4) & 0xf]);
}
break;
}
- command_print(cmd_ctx, "\t%s\tType is 0x%02x, %s, %s",
- tabs, devtype & 0xff,
+ command_print(cmd_ctx, "\t\tType is 0x%02x, %s, %s",
+ devtype & 0xff,
major, subtype);
/* REVISIT also show 0xfc8 DevId */
}
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
command_print(cmd_ctx,
- "\t%s\tCID3 0%02x"
+ "\t\tCID3 0%02x"
", CID2 0%02x"
", CID1 0%02x"
", CID0 0%02x",
- tabs,
(int)c_cid3,
(int)c_cid2,
(int)c_cid1,
(int)c_cid0);
command_print(cmd_ctx,
- "\t%s\tPeripheral ID[4..0] = hex "
- "%02x %02x %02x %02x %02x", tabs,
+ "\t\tPeripheral ID[4..0] = hex "
+ "%02x %02x %02x %02x %02x",
(int)c_pid4, (int)c_pid3, (int)c_pid2,
(int)c_pid1, (int)c_pid0);
type = "Cortex-R4 ETM";
full = "(Embedded Trace)";
break;
+ case 0x950:
+ type = "CoreSight Component";
+ full = "(unidentified Cortex-A9 component)";
+ break;
+ case 0x9a0:
+ type = "CoreSight PMU";
+ full = "(Performance Monitoring Unit)";
+ break;
case 0x9a1:
type = "Cortex-M4 TPUI";
full = "(Trace Port Interface Unit)";
full = "";
break;
}
- command_print(cmd_ctx, "\t%s\tPart is %s %s",
- tabs, type, full);
+ command_print(cmd_ctx, "\t\tPart is %s %s",
+ type, full);
/* ROM Table? */
if (((c_cid1 >> 4) & 0x0f) == 1) {
}
} else {
if (romentry)
- command_print(cmd_ctx, "\t%s\tComponent not present", tabs);
+ command_print(cmd_ctx, "\t\tComponent not present");
else
break;
}
return retval;
}
+COMMAND_HANDLER(dap_ti_be_32_quirks_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target_to_arm(target);
+ struct adiv5_dap *dap = arm->dap;
+
+ uint32_t enable = dap->ti_be_32_quirks;
+
+ switch (CMD_ARGC) {
+ case 0:
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
+ if (enable > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ dap->ti_be_32_quirks = enable;
+ command_print(CMD_CTX, "TI BE-32 quirks mode %s",
+ enable ? "enabled" : "disabled");
+
+ return 0;
+}
+
static const struct command_registration dap_commands[] = {
{
.name = "info",
"bus access [0-255]",
.usage = "[cycles]",
},
+ {
+ .name = "ti_be_32_quirks",
+ .handler = dap_ti_be_32_quirks_command,
+ .mode = COMMAND_CONFIG,
+ .help = "set/get quirks mode for TI TMS450/TMS570 processors",
+ .usage = "[enable]",
+ },
COMMAND_REGISTRATION_DONE
};
projects / openocd / blobdiff