X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=inline;f=board%2Fesd%2Fcommon%2Fesd405ep_nand.c;h=51ac10c8c0a30e7e356c6f024320854490e9e87c;hb=d4db3b86a5e090e21db710bedbbe3e50d4c56428;hp=7bf68473d28372256ed13b5a64902d82945713f2;hpb=a44e7a97c8cbbac3cbc32376dcaad0ec1f76f604;p=u-boot

diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
index 7bf68473d2..51ac10c8c0 100644
--- a/board/esd/common/esd405ep_nand.c
+++ b/board/esd/common/esd405ep_nand.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2007
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -30,28 +14,26 @@
 /*
  * hardware specific access to control-lines
  */
-static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	switch(cmd) {
-	case NAND_CTL_SETCLE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
-		break;
-	case NAND_CTL_CLRCLE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
-		break;
-	case NAND_CTL_SETALE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
-		break;
-	case NAND_CTL_CLRALE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
-		break;
-	case NAND_CTL_SETNCE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
-		break;
-	case NAND_CTL_CLRNCE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
-		break;
+	struct nand_chip *this = mtd_to_nand(mtd);
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
+		if ( ctrl & NAND_ALE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
+		if ( ctrl & NAND_NCE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 
@@ -60,7 +42,7 @@ static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
  */
 static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
 {
-	if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+	if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
 		return 1;
 	return 0;
 }
@@ -71,15 +53,15 @@ int board_nand_init(struct nand_chip *nand)
 	/*
 	 * Set NAND-FLASH GPIO signals to defaults
 	 */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 
 	/*
 	 * Initialize nand_chip structure
 	 */
-	nand->hwcontrol = esd405ep_nand_hwcontrol;
+	nand->cmd_ctrl = esd405ep_nand_hwcontrol;
 	nand->dev_ready = esd405ep_nand_device_ready;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->chip_delay = NAND_BIG_DELAY_US;
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	return 0;