X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=inline;f=board%2Ffreescale%2Fcommon%2Fns_access.c;h=81c921122e8f65053e7e581426fc8083a62b44e1;hb=3759b5b649aa77bcbdf8852ebd80de2090addc45;hp=d7de9822d031ee0a2eba26530043fe5db94ec389;hpb=e87f3b308c454f6e78b02da857936c7d012c385b;p=u-boot

diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index d7de9822d0..81c921122e 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -6,25 +6,65 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <fsl_csu.h>
 #include <asm/arch/ns_access.h>
+#include <asm/arch/fsl_serdes.h>
 
-void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
 {
 	u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
 	u32 *reg;
-	uint32_t val;
+	uint32_t tmp;
+
+	reg = base + ns_dev->ind / 2;
+	tmp = in_be32(reg);
+	if (ns_dev->ind % 2 == 0) {
+		tmp &= 0x0000ffff;
+		tmp |= val << 16;
+	} else {
+		tmp &= 0xffff0000;
+		tmp |= val;
+	}
+
+	out_be32(reg, tmp);
+}
+
+static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
 	int i;
 
-	for (i = 0; i < num; i++) {
-		reg = base + ns_dev[i].ind / 2;
-		val = in_be32(reg);
-		if (ns_dev[i].ind % 2 == 0) {
-			val &= 0x0000ffff;
-			val |= ns_dev[i].val << 16;
-		} else {
-			val &= 0xffff0000;
-			val |= ns_dev[i].val;
-		}
-		out_be32(reg, val);
+	for (i = 0; i < num; i++)
+		set_devices_ns_access(ns_dev + i, ns_dev[i].val);
+}
+
+void enable_layerscape_ns_access(void)
+{
+	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+}
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+	switch (pcie) {
+#ifdef CONFIG_PCIE1
+	case PCIE1:
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
+		return;
+#endif
+#ifdef CONFIG_PCIE2
+	case PCIE2:
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
+		return;
+#endif
+#ifdef CONFIG_PCIE3
+	case PCIE3:
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
+		return;
+#endif
+	default:
+		debug("The PCIE%d doesn't exist!\n", pcie);
+		return;
 	}
 }