X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=inline;f=include%2Fasm-ppc%2Fimmap_85xx.h;h=da97cd4c8cbebda461759370137b510691515802;hb=ef7d30b14394e4c4a153118f5845760cadada02a;hp=3506aec5ec5e5ebef5d7f162ac2d164c6ec6d649;hpb=5893b3d0a4084f87a06a5d3dc03db91206818941;p=u-boot diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 3506aec5ec..da97cd4c8c 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -57,7 +57,7 @@ typedef struct ccsr_local_ecm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[780]; // XXX: LAW 8, LAW9 for 8572 + char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */ uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ char res21[12]; uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ @@ -106,8 +106,8 @@ typedef struct ccsr_ddr { char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res7[20]; - uint init_address; /* 0x2148 - DDR training initialization address */ - uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + uint init_addr; /* 0x2148 - DDR training initialization address */ + uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ char res8_1[16]; uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ @@ -1570,7 +1570,9 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - char res1[12]; + uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 + char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; uint gpiocr; /* 0xe0030 - GPIO control register */