X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=arch%2Farm%2Fdts%2Fzynq-zc770-xm010.dts;h=0c364dfcc14ff4bf7717c066a120219098fae8fd;hb=051a8ad7bb9fa05c4b2ae74d9059d4f7157d5fd1;hp=bf107e308a6a77a53f60f17a107fad4e598760ae;hpb=891b487098ee2169a16b1bbb354aaef28aa90630;p=u-boot diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index bf107e308a..0c364dfcc1 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -1,28 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM010 board DTS * - * Copyright (C) 2013 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2013-2018 Xilinx, Inc. */ /dts-v1/; #include "zynq-7000.dtsi" / { - model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; spi1 = &spi1; }; - memory { + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; }; + +}; + +&qspi { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; }; &spi1 { status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@0 { + compatible = "sst25wf080"; + reg = <1>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@test { + label = "spi-flash"; + reg = <0x0 0x100000>; + }; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; };