X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=arch%2Farm%2Finclude%2Fasm%2Farch-am33xx%2Fclock.h;h=dc7a9b188d34f75027c6d5f22e7767640c8bdeba;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=4af6b57e42f5528c7ed2e78796b654a94f179ec1;hpb=64ce2fbd6c9ebb68e274ae1b3c449e1cae86c5b6;p=u-boot

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 4af6b57e42..dc7a9b188d 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -1,19 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * clock.h
  *
  * clock header
  *
  * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef _CLOCKS_H_
 #define _CLOCKS_H_
 
 #include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/hardware.h>
 
-#ifdef CONFIG_TI81XX
+#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
 #include <asm/arch/clock_ti81xx.h>
 #endif
 
@@ -44,6 +44,9 @@
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_SSC_EN_SHIFT		12
 #define CM_CLKMODE_DPLL_SSC_EN_MASK		(1 << 12)
+#define CM_CLKMODE_DPLL_SSC_ACK_MASK		(1 << 13)
+#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK	(1 << 14)
+#define CM_CLKMODE_DPLL_SSC_TYPE_MASK		(1 << 15)
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
@@ -100,6 +103,13 @@ extern const struct dpll_regs dpll_mpu_regs;
 extern const struct dpll_regs dpll_core_regs;
 extern const struct dpll_regs dpll_per_regs;
 extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_regs dpll_disp_regs;
+extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
+extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
 
 extern struct cm_wkuppll *const cmwkup;
 
@@ -111,6 +121,14 @@ void scale_vcores(void);
 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 void prcm_init(void);
 void enable_basic_clocks(void);
+
+void rtc_only_update_board_type(u32 btype);
+u32 rtc_only_get_board_type(void);
+void rtc_only_prcm_init(void);
+void rtc_only_enable_basic_clocks(void);
+
 void do_enable_clocks(u32 *const *, u32 *const *, u8);
+void do_disable_clocks(u32 *const *, u32 *const *, u8);
 
+void set_mpu_spreadspectrum(int permille);
 #endif