X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=arch%2Farm%2Fmach-keystone%2Finclude%2Fmach%2Fclock_defs.h;h=f8d61d6ef1f2f82f20527ad5976e4786c94e1e73;hb=0fba27b69033276b23711a3ea8c06ab65382b14b;hp=85a046b89a92c11620512795cbb5210cb97eaa07;hpb=dc7de222aa82cc962f15b5d04e1e4c6b0ab62398;p=u-boot diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h index 85a046b89a..f8d61d6ef1 100644 --- a/arch/arm/mach-keystone/include/mach/clock_defs.h +++ b/arch/arm/mach-keystone/include/mach/clock_defs.h @@ -11,8 +11,6 @@ #include -#define BIT(x) (1 << (x)) - /* PLL Control Registers */ struct pllctl_regs { u32 ctl; /* 00 */ @@ -70,42 +68,66 @@ static struct pllctl_regs *pllctl_regs[] = { #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) /* PLLCTL Bits */ -#define PLLCTL_BYPASS BIT(23) -#define PLL_PLLRST BIT(14) -#define PLLCTL_PAPLL BIT(13) -#define PLLCTL_CLKMODE BIT(8) -#define PLLCTL_PLLSELB BIT(7) -#define PLLCTL_ENSAT BIT(6) -#define PLLCTL_PLLENSRC BIT(5) -#define PLLCTL_PLLDIS BIT(4) -#define PLLCTL_PLLRST BIT(3) -#define PLLCTL_PLLPWRDN BIT(1) -#define PLLCTL_PLLEN BIT(0) -#define PLLSTAT_GO BIT(0) - -#define MAIN_ENSAT_OFFSET 6 - -#define PLLDIV_ENABLE BIT(15) - -#define PLL_DIV_MASK 0x3f -#define PLL_MULT_MASK 0x1fff -#define PLL_MULT_SHIFT 6 -#define PLLM_MULT_HI_MASK 0x7f -#define PLLM_MULT_HI_SHIFT 12 -#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) -#define PLLM_MULT_LO_MASK 0x3f -#define PLL_CLKOD_MASK 0xf -#define PLL_CLKOD_SHIFT 19 -#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) -#define PLL_BWADJ_LO_MASK 0xff -#define PLL_BWADJ_LO_SHIFT 24 -#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) -#define PLL_BWADJ_HI_MASK 0xf - -#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) -#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) -#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) -#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) -#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) +#define PLLCTL_PLLENSRC_SHIF 5 +#define PLLCTL_PLLENSRC_MASK BIT(5) +#define PLLCTL_PLLRST_SHIFT 3 +#define PLLCTL_PLLRST_MASK BIT(3) +#define PLLCTL_PLLPWRDN_SHIFT 1 +#define PLLCTL_PLLPWRDN_MASK BIT(1) +#define PLLCTL_PLLEN_SHIFT 0 +#define PLLCTL_PLLEN_MASK BIT(0) + +/* SECCTL Bits */ +#define SECCTL_BYPASS_SHIFT 23 +#define SECCTL_BYPASS_MASK BIT(23) +#define SECCTL_OP_DIV_SHIFT 19 +#define SECCTL_OP_DIV_MASK (0xf << 19) + +/* PLLM Bits */ +#define PLLM_MULT_LO_SHIFT 0 +#define PLLM_MULT_LO_MASK 0x3f +#define PLLM_MULT_LO_BITS 6 + +/* PLLDIVn Bits */ +#define PLLDIV_ENABLE_SHIFT 15 +#define PLLDIV_ENABLE_MASK BIT(15) +#define PLLDIV_RATIO_SHIFT 0x0 +#define PLLDIV_RATIO_MASK 0xff +#define PLLDIV_MAX 16 + +/* PLLCMD Bits */ +#define PLLCMD_GOSET_SHIFT 0 +#define PLLCMD_GOSET_MASK BIT(0) + +/* PLLSTAT Bits */ +#define PLLSTAT_GOSTAT_SHIFT 0 +#define PLLSTAT_GOSTAT_MASK BIT(0) + +/* Device Config PLLCTL0 */ +#define CFG_PLLCTL0_BWADJ_SHIFT 24 +#define CFG_PLLCTL0_BWADJ_MASK (0xff << 24) +#define CFG_PLLCTL0_BWADJ_BITS 8 +#define CFG_PLLCTL0_BYPASS_SHIFT 23 +#define CFG_PLLCTL0_BYPASS_MASK BIT(23) +#define CFG_PLLCTL0_CLKOD_SHIFT 19 +#define CFG_PLLCTL0_CLKOD_MASK (0xf << 19) +#define CFG_PLLCTL0_PLLM_HI_SHIFT 12 +#define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12) +#define CFG_PLLCTL0_PLLM_SHIFT 6 +#define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6) +#define CFG_PLLCTL0_PLLD_SHIFT 0 +#define CFG_PLLCTL0_PLLD_MASK 0x3f + +/* Device Config PLLCTL1 */ +#define CFG_PLLCTL1_RST_SHIFT 14 +#define CFG_PLLCTL1_RST_MASK BIT(14) +#define CFG_PLLCTL1_PAPLL_SHIFT 13 +#define CFG_PLLCTL1_PAPLL_MASK BIT(13) +#define CFG_PLLCTL1_ENSAT_SHIFT 6 +#define CFG_PLLCTL1_ENSAT_MASK BIT(6) +#define CFG_PLLCTL1_BWADJ_SHIFT 0 +#define CFG_PLLCTL1_BWADJ_MASK 0xf + +#define MISC_CTL1_ARM_PLL_EN BIT(13) #endif /* _CLOCK_DEFS_H_ */