X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=arch%2Farm%2Fmach-socfpga%2Freset_manager.c;h=1186358a71a3259715173ad95ac4fb74a656db70;hb=2df7b2aadf375fc3d2f336fab8eb41556b997567;hp=18af25ced1ae2311aca0e5b73e1c36b479b833eb;hpb=a71df7aa4fa775199280bba19072bd232cc35cb1;p=u-boot

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 18af25ced1..1186358a71 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -39,6 +39,19 @@ void socfpga_per_reset(u32 reset, int set)
 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 }
 
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+	writel(~l4wd0, &reset_manager_base->per_mod_reset);
+	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+}
+
 /*
  * Write the reset manager register to cause reset
  */
@@ -85,10 +98,10 @@ void socfpga_bridges_reset(int enable)
 		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
 	} else {
 		/* Check signal from FPGA. */
-		if (fpgamgr_poll_fpga_ready()) {
-			/* FPGA not ready. Wait for watchdog timeout. */
-			printf("%s: fpga not ready, hanging.\n", __func__);
-			hang();
+		if (!fpgamgr_test_fpga_ready()) {
+			/* FPGA not ready, do nothing. */
+			printf("%s: FPGA not ready, aborting.\n", __func__);
+			return;
 		}
 
 		/* brdmodrst */