X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=arch%2Fpowerpc%2Fcpu%2Fmpc8xx%2Fcpu_init.c;h=f621d6285ceb730b0380c1ee8e2988aa0a1214fe;hb=d19f6a60ec9a342a4dbb38396d354562b4ce3c5e;hp=53f873d1abf6052c0ef9674b2f62f979af930eaa;hpb=aaf5e825606a70ddc8fca8e366d8c16a6fd3cc7c;p=u-boot diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 53f873d1ab..f621d6285c 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -29,12 +29,10 @@ void cpm_load_patch (volatile immap_t * immr); */ void cpu_init_f (volatile immap_t * immr) { -#ifndef CONFIG_MBX volatile memctl8xx_t *memctl = &immr->im_memctl; # ifdef CONFIG_SYS_PLPRCR ulong mfmask; # endif -#endif ulong reg; /* SYPCR - contains watchdog control (11-9) */ @@ -46,11 +44,7 @@ void cpu_init_f (volatile immap_t * immr) #endif /* CONFIG_WATCHDOG */ /* SIUMCR - contains debug pin configuration (11-6) */ -#ifndef CONFIG_SVM_SC8xx immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; -#else - immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; -#endif /* initialize timebase status and control register (11-26) */ /* unlock TBSCRK */ @@ -74,8 +68,6 @@ void cpu_init_f (volatile immap_t * immr) immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; -#ifndef CONFIG_MBX /* MBX board does things different */ - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF @@ -133,23 +125,6 @@ void cpu_init_f (volatile immap_t * immr) * I owe him a free beer. - wd] */ -#if defined(CONFIG_HERMES) || \ - defined(CONFIG_ICU862) || \ - defined(CONFIG_IP860) || \ - defined(CONFIG_IVML24) || \ - defined(CONFIG_IVMS8) || \ - defined(CONFIG_LWMON) || \ - defined(CONFIG_MHPC) || \ - defined(CONFIG_R360MPI) || \ - defined(CONFIG_RMU) || \ - defined(CONFIG_RPXCLASSIC) || \ - defined(CONFIG_RPXLITE) || \ - defined(CONFIG_SPC1920) || \ - defined(CONFIG_SPD823TS) - - memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; -#endif - #if defined(CONFIG_SYS_OR0_REMAP) memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; #endif @@ -169,10 +144,6 @@ void cpu_init_f (volatile immap_t * immr) memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif -#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ - memctl->memc_br0 = 0; -#endif - #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; @@ -203,8 +174,6 @@ void cpu_init_f (volatile immap_t * immr) memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif -#endif /* ! CONFIG_MBX */ - /* * Reset CPM */ @@ -213,24 +182,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); -#ifdef CONFIG_MBX - /* - * on the MBX, things are a little bit different: - * - we need to read the VPD to get board information - * - the plprcr is set up dynamically - * - the memory controller is set up dynamically - */ - mbx_init (); -#endif /* CONFIG_MBX */ - -#ifdef CONFIG_RPXCLASSIC - rpxclassic_init (); -#endif - -#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM) - rpxlite_init (); -#endif - #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ /* write config value */ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;