X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=arch%2Fx86%2Fcpu%2Fsc520%2Fsc520_ssi.c;h=cc601e56e48328e8998c3e47b4beb229f7779a39;hb=109ad143f8f2a948dc6628f55dbb6a8905087bfe;hp=ac58d259705e24e96983376fd32b593397754422;hpb=f16b608ae7d0c4611d3a41d2570616a498e64d4c;p=u-boot

diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c
index ac58d25970..cc601e56e4 100644
--- a/arch/x86/cpu/sc520/sc520_ssi.c
+++ b/arch/x86/cpu/sc520/sc520_ssi.c
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,42 +23,38 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/ic/ssi.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/ssi.h>
+#include <asm/arch/sc520.h>
 
 int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
 {
-	u8 temp=0;
+	u8 temp = 0;
 
-	if (freq >= 8192) {
+	if (freq >= 8192)
 		temp |= CTL_CLK_SEL_4;
-	} else if (freq >= 4096) {
+	else if (freq >= 4096)
 		temp |= CTL_CLK_SEL_8;
-	} else if (freq >= 2048) {
+	else if (freq >= 2048)
 		temp |= CTL_CLK_SEL_16;
-	} else if (freq >= 1024) {
+	else if (freq >= 1024)
 		temp |= CTL_CLK_SEL_32;
-	} else if (freq >= 512) {
+	else if (freq >= 512)
 		temp |= CTL_CLK_SEL_64;
-	} else if (freq >= 256) {
+	else if (freq >= 256)
 		temp |= CTL_CLK_SEL_128;
-	} else if (freq >= 128) {
+	else if (freq >= 128)
 		temp |= CTL_CLK_SEL_256;
-	} else {
+	else
 		temp |= CTL_CLK_SEL_512;
-	}
 
-	if (!lsb_first) {
+	if (!lsb_first)
 		temp |= MSBF_ENB;
-	}
 
-	if (inv_clock) {
+	if (inv_clock)
 		temp |= CLK_INV_ENB;
-	}
 
-	if (inv_phase) {
+	if (inv_phase)
 		temp |= PHS_INV_ENB;
-	}
 
 	writeb(temp, &sc520_mmcr->ssictl);
 
@@ -68,9 +64,11 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
 u8 ssi_txrx_byte(u8 data)
 {
 	writeb(data, &sc520_mmcr->ssixmit);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+		;
 	writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+		;
 
 	return readb(&sc520_mmcr->ssircv);
 }
@@ -78,15 +76,18 @@ u8 ssi_txrx_byte(u8 data)
 void ssi_tx_byte(u8 data)
 {
 	writeb(data, &sc520_mmcr->ssixmit);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+		;
 	writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
 }
 
 u8 ssi_rx_byte(void)
 {
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+		;
 	writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+		;
 
 	return readb(&sc520_mmcr->ssircv);
 }