X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=arch%2Fx86%2Flib%2Fzimage.c;h=1b33c771391f49ffe82864ff1582bdfd07e5e97d;hb=fc4f5cccd87abf4c72b13f64b49719fde9107cad;hp=a1ec57e8d3ea478e1d75babac788f71eafd89e18;hpb=cc35734358540a1bbaf042fdf9f4cb2de17389ed;p=u-boot

diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index a1ec57e8d3..1b33c77139 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -42,32 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define COMMAND_LINE_SIZE	2048
 
-/*
- * Install a default e820 table with 3 entries as follows:
- *
- *	0x000000-0x0a0000	Useable RAM
- *	0x0a0000-0x100000	Reserved for ISA
- *	0x100000-gd->ram_size	Useable RAM
- */
-__weak unsigned install_e820_map(unsigned max_entries,
-				 struct e820entry *entries)
-{
-	entries[0].addr = 0;
-	entries[0].size = ISA_START_ADDRESS;
-	entries[0].type = E820_RAM;
-	entries[1].addr = ISA_START_ADDRESS;
-	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[1].type = E820_RESERVED;
-	entries[2].addr = ISA_END_ADDRESS;
-	entries[2].size = gd->ram_size - ISA_END_ADDRESS;
-	entries[2].type = E820_RAM;
-	entries[3].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[3].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[3].type = E820_RESERVED;
-
-	return 4;
-}
-
 static void build_command_line(char *command_line, int auto_boot)
 {
 	char *env_command_line;