X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=board%2Fcsb272%2Fcsb272.c;h=1ed3e1b6a4e5c6c36b3eeff4c27e28fc0fc58347;hb=e6441c4f4070aac6825f5b195f38dfe1da53675c;hp=11596d2b7e9636b8769eedc28057729ceb9db528;hpb=156feb90d200f186cdfd856d7f6f1878bb1bec1e;p=u-boot

diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index 11596d2b7e..1ed3e1b6a4 100644
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -87,15 +87,15 @@ int board_early_init_f(void)
    |
    +-------------------------------------------------------------------------*/
 
-	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
-	mtdcr (uicer, 0x00000000);   /* disable all ints */
-	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
-	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
 
-	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
 
 	return 0; /* success */
 }
@@ -129,35 +129,35 @@ phys_size_t initdram (int board_type)
 	/*
 	 * ToDo: Move the asm init routine sdram_init() to this C file,
 	 * or even better use some common ppc4xx code available
-	 * in cpu/ppc4xx
+	 * in arch/powerpc/cpu/ppc4xx
 	 */
 	sdram_init();
 
 	tot_size = 0;
 
-	mtdcr (memcfga, mem_mb0cf);
-	tmp = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
 	if (tmp & 0x00000001) {
 		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 		tot_size += bank_size;
 	}
 
-	mtdcr (memcfga, mem_mb1cf);
-	tmp = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
 	if (tmp & 0x00000001) {
 		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 		tot_size += bank_size;
 	}
 
-	mtdcr (memcfga, mem_mb2cf);
-	tmp = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
 	if (tmp & 0x00000001) {
 		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 		tot_size += bank_size;
 	}
 
-	mtdcr (memcfga, mem_mb3cf);
-	tmp = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+	tmp = mfdcr (SDRAM0_CFGDATA);
 	if (tmp & 0x00000001) {
 		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 		tot_size += bank_size;