X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=board%2Ffreescale%2Fmpc837xemds%2Fpci.c;h=39c40e5cc95fdcc61905df799cb821b6424588dc;hb=45fe3809b9923b92f221d70eb45ae071059fd5e0;hp=31116b31ce5d09313d3a7640f9d27c2fd923d3d8;hpb=ef29884b2708a6cce3b77f4ccaeea193d4e02c22;p=u-boot

diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
index 31116b31ce..39c40e5cc9 100644
--- a/board/freescale/mpc837xemds/pci.c
+++ b/board/freescale/mpc837xemds/pci.c
@@ -1,13 +1,7 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <asm/mmu.h>
@@ -18,9 +12,8 @@
 #include <i2c.h>
 #include <fdt_support.h>
 #include <asm/fsl_i2c.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
 
-#if defined(CONFIG_PCI)
 static struct pci_region pci_regions[] = {
 	{
 		bus_start: CONFIG_SYS_PCI_MEM_BASE,
@@ -109,12 +102,19 @@ void pci_init_board(void)
 
 	udelay(2000);
 
-	mpc83xx_pci_init(1, reg, 0);
+	mpc83xx_pci_init(1, reg);
 skip_pci:
 	/* There is no PEX in MPC8379 parts. */
 	if (PARTID_NO_E(spridr) == SPR_8379)
 		return;
 
+	if (pex2)
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+	else
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
 	/* Configure the clock for PCIE controller */
 	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
 				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
@@ -132,14 +132,7 @@ skip_pci:
 	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
 	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
 
-	if (pex2)
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-	else
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
+	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
 }
 
 void ft_pcie_fixup(void *blob, bd_t *bd)
@@ -152,4 +145,3 @@ void ft_pcie_fixup(void *blob, bd_t *bd)
 	do_fixup_by_path(blob, "pci2", "status", status,
 			 strlen(status) + 1, 1);
 }
-#endif /* CONFIG_PCI */