X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=board%2Fgen860t%2Ffpga.c;h=37788d5396a86af3b4ed1fd717ebca74bf35b906;hb=79830d591afb758be8556396949d433fee1527c2;hp=2c4fbf14c8f9e4c7aff287e997d108f1f1849cba;hpb=c609719b8d1b2dca590e0ed499016d041203e403;p=u-boot

diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 2c4fbf14c8..37788d5396 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -72,30 +72,27 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
 };
 
 Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	{ Xilinx_Virtex2,
-	  slave_selectmap,
-	  XILINX_XC2V3000_SIZE,
-	  (void *)&fpga_fns,
-	  0
-	}
+	{Xilinx_Virtex2,
+	 slave_selectmap,
+	 XILINX_XC2V3000_SIZE,
+	 (void *) &fpga_fns,
+	 0}
 };
 
 /*
  * Display FPGA revision information
  */
-void
-print_fpga_revision(void)
+void print_fpga_revision (void)
 {
-	vu_long *rev_p = (vu_long *)0x60000008;
-
-	printf("FPGA Revision 0x%.8lx"
-		   " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
-		   *rev_p,
-		   ((*rev_p >> 28) & 0xf),
-		   ((*rev_p >> 20) & 0xff),
-		   ((*rev_p >> 12) & 0xff),
-		   ((*rev_p >> 8) & 0xf),
-		   (*rev_p & 0xff));
+	vu_long *rev_p = (vu_long *) 0x60000008;
+
+	printf ("FPGA Revision 0x%.8lx"
+		" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
+		*rev_p,
+		((*rev_p >> 28) & 0xf),
+		((*rev_p >> 20) & 0xff),
+		((*rev_p >> 12) & 0xff),
+		((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
 }
 
 
@@ -106,10 +103,9 @@ print_fpga_revision(void)
  * problems with bus charging.
  * Return 0 on failure, 1 on success.
  */
-int
-test_fpga_ibtr(void)
+int test_fpga_ibtr (void)
 {
-	vu_long *ibtr_p = (vu_long *)0x60000010;
+	vu_long *ibtr_p = (vu_long *) 0x60000010;
 	vu_long readback;
 	vu_long compare;
 	int i;
@@ -118,40 +114,41 @@ test_fpga_ibtr(void)
 	int pass = 1;
 
 	static const ulong bitpattern[] = {
-		0xdeadbeef,	/* magic ID pattern for debug	*/
-		0x00000001,	/* single bit					*/
-		0x00000003,	/* two adjacent bits			*/
-		0x00000007,	/* three adjacent bits			*/
-		0x0000000F,	/* four adjacent bits			*/
-		0x00000005,	/* two non-adjacent bits		*/
-		0x00000015,	/* three non-adjacent bits		*/
-		0x00000055,	/* four non-adjacent bits		*/
-		0xaaaaaaaa,	/* alternating 1/0				*/
+		0xdeadbeef,	/* magic ID pattern for debug   */
+		0x00000001,	/* single bit                                   */
+		0x00000003,	/* two adjacent bits                    */
+		0x00000007,	/* three adjacent bits                  */
+		0x0000000F,	/* four adjacent bits                   */
+		0x00000005,	/* two non-adjacent bits                */
+		0x00000015,	/* three non-adjacent bits              */
+		0x00000055,	/* four non-adjacent bits               */
+		0xaaaaaaaa,	/* alternating 1/0                              */
 	};
 
 	for (i = 0; i < 1024; i++) {
 		for (j = 0; j < 31; j++) {
-			for (k = 0; k < sizeof(bitpattern)/sizeof(bitpattern[0]); k++) {
+			for (k = 0;
+			     k < sizeof (bitpattern) / sizeof (bitpattern[0]);
+			     k++) {
 				*ibtr_p = compare = (bitpattern[k] << j);
 				readback = *ibtr_p;
 				if (readback != ~compare) {
-					printf("%s:%d: FPGA test fail: expected 0x%.8lx"
-						   " actual 0x%.8lx\n",
-						   __FUNCTION__, __LINE__, ~compare, readback);
+					printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
 					pass = 0;
 					break;
 				}
 			}
-			if (!pass) break;
+			if (!pass)
+				break;
 		}
-		if (!pass) break;
+		if (!pass)
+			break;
 	}
 	if (pass) {
-		printf("FPGA inverting bus test passed\n");
-		print_fpga_revision();
-	}
-	else {
-		printf("** FPGA inverting bus test failed\n");
+		printf ("FPGA inverting bus test passed\n");
+		print_fpga_revision ();
+	} else {
+		printf ("** FPGA inverting bus test failed\n");
 	}
 	return pass;
 }
@@ -160,19 +157,17 @@ test_fpga_ibtr(void)
 /*
  * Set the active-low FPGA reset signal.
  */
-void
-fpga_reset(int assert)
+void fpga_reset (int assert)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: RESET ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
 	if (assert) {
 		immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
-		PRINTF("asserted\n");
-	}
-	else {
+		PRINTF ("asserted\n");
+	} else {
 		immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
-		PRINTF("deasserted\n");
+		PRINTF ("deasserted\n");
 	}
 }
 
@@ -181,54 +176,52 @@ fpga_reset(int assert)
  * Initialize the SelectMap interface.  We assume that the mode and the
  * initial state of all of the port pins have already been set!
  */
-void
-fpga_selectmap_init(void)
+void fpga_selectmap_init (void)
 {
-	PRINTF("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__);
-	fpga_pgm_fn(FALSE, FALSE, 0);   /* make sure program pin is inactive */
+	PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
+		__LINE__);
+	fpga_pgm_fn (FALSE, FALSE, 0);	/* make sure program pin is inactive */
 }
 
 
 /*
  * Initialize the fpga.  Return 1 on success, 0 on failure.
  */
-int
-gen860t_init_fpga(void)
+int gen860t_init_fpga (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
 	int i;
 
-	PRINTF("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
-			__FUNCTION__, __LINE__, gd->reloc_off);
-	fpga_init(gd->reloc_off);
-	fpga_selectmap_init();
+	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
+	fpga_init (gd->reloc_off);
+	fpga_selectmap_init ();
 
-	for(i=0; i < CONFIG_FPGA_COUNT; i++) {
-		PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
-		fpga_add(fpga_xilinx, &fpga[i]);
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add (fpga_xilinx, &fpga[i]);
 	}
- 	return 1;
+	return 1;
 }
 
 
 /*
  * Set the FPGA's active-low SelectMap program line to the specified level
  */
-int
-fpga_pgm_fn(int assert, int flush, int cookie)
+int fpga_pgm_fn (int assert, int flush, int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
 
 	if (assert) {
-		immap->im_ioport.iop_padat &= ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
-		PRINTF("asserted\n");
-	}
-	else {
-		immap->im_ioport.iop_padat |= (0x8000 >> FPGA_PROGRAM_BIT_NUM);
-		PRINTF("deasserted\n");
+		immap->im_ioport.iop_padat &=
+			~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("asserted\n");
+	} else {
+		immap->im_ioport.iop_padat |=
+			(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("deasserted\n");
 	}
 	return assert;
 }
@@ -238,18 +231,16 @@ fpga_pgm_fn(int assert, int flush, int cookie)
  * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
  * asserted (low).
  */
-int
-fpga_init_fn(int cookie)
+int fpga_init_fn (int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-	if(immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
-		PRINTF("high\n");
+	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
+		PRINTF ("high\n");
 		return 0;
-	}
-	else {
-		PRINTF("low\n");
+	} else {
+		PRINTF ("low\n");
 		return 1;
 	}
 }
@@ -258,18 +249,16 @@ fpga_init_fn(int cookie)
 /*
  * Test the state of the active-high FPGA DONE pin
  */
-int
-fpga_done_fn(int cookie)
+int fpga_done_fn (int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
-	PRINTF("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
 	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
-		PRINTF("high\n");
+		PRINTF ("high\n");
 		return FPGA_SUCCESS;
-	}
-	else {
-		PRINTF("low\n");
+	} else {
+		PRINTF ("low\n");
 		return FPGA_FAIL;
 	}
 }
@@ -278,43 +267,40 @@ fpga_done_fn(int cookie)
 /*
  * Read FPGA SelectMap data.
  */
-int
-fpga_read_data_fn(unsigned char *data, int cookie)
+int fpga_read_data_fn (unsigned char *data, int cookie)
 {
-	vu_char *p = (vu_char *)SELECTMAP_BASE;
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
 
 	*data = *p;
 #if 0
-	PRINTF("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int)data, data);
+	PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
 #endif
-	return (int)data;
+	return (int) data;
 }
 
 
 /*
  * Write data to the FPGA SelectMap port
  */
-int
-fpga_write_data_fn(unsigned char data, int flush, int cookie)
+int fpga_write_data_fn (unsigned char data, int flush, int cookie)
 {
-	vu_char *p = (vu_char *)SELECTMAP_BASE;
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
 
 #if 0
-	PRINTF("%s: Write Data 0x%x\n", __FUNCTION__, (int)data);
+	PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
 #endif
 	*p = data;
-	return (int)data;
+	return (int) data;
 }
 
 
 /*
  * Abort and FPGA operation
  */
-int
-fpga_abort_fn(int cookie)
+int fpga_abort_fn (int cookie)
 {
-	PRINTF("%s:%d: FPGA program sequence aborted\n",
-		   __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: FPGA program sequence aborted\n",
+		__FUNCTION__, __LINE__);
 	return FPGA_FAIL;
 }
 
@@ -324,11 +310,10 @@ fpga_abort_fn(int cookie)
  * FPGA reset is asserted to keep the FPGA from starting up after
  * configuration.
  */
-int
-fpga_pre_config_fn(int cookie)
+int fpga_pre_config_fn (int cookie)
 {
-	PRINTF("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(TRUE);
+	PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
 	return 0;
 }
 
@@ -337,22 +322,21 @@ fpga_pre_config_fn(int cookie)
  * FPGA post configuration function. Blip the FPGA reset line and then see if
  * the FPGA appears to be running.
  */
-int
-fpga_post_config_fn(int cookie)
+int fpga_post_config_fn (int cookie)
 {
 	int rc;
 
-	PRINTF("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(TRUE);
-	udelay(1000);
-	fpga_reset(FALSE);
+	PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
+	udelay (1000);
+	fpga_reset (FALSE);
 	udelay (1000);
 
 	/*
 	 * Use the FPGA,s inverting bus test register to do a simple test of the
 	 * processor interface.
 	 */
-	rc = test_fpga_ibtr();
+	rc = test_fpga_ibtr ();
 	return rc;
 }
 
@@ -367,32 +351,27 @@ fpga_post_config_fn(int cookie)
  * going low during configuration, so there is no need for a separate error
  * function.
  */
-int
-fpga_clk_fn(int assert_clk, int flush, int cookie)
+int fpga_clk_fn (int assert_clk, int flush, int cookie)
 {
 	return assert_clk;
 }
 
-int
-fpga_cs_fn(int assert_cs, int flush, int cookie)
+int fpga_cs_fn (int assert_cs, int flush, int cookie)
 {
 	return assert_cs;
 }
 
-int
-fpga_wr_fn(int assert_write, int flush, int cookie)
+int fpga_wr_fn (int assert_write, int flush, int cookie)
 {
 	return assert_write;
 }
 
-int
-fpga_err_fn(int cookie)
+int fpga_err_fn (int cookie)
 {
 	return 0;
 }
 
-int
-fpga_busy_fn(int cookie)
+int fpga_busy_fn (int cookie)
 {
 	return 0;
 }