X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=board%2Fmcc200%2Fmcc200.c;h=af047e2a0772a281303f99590ddc79fe1739bc12;hb=cfc67116a706fd18b8f6a9c11a16753c5626d689;hp=71a691b5dbf1fb171b62ad823b603aeef65d8dbb;hpb=64cd52efd1dc51a4a5a0cf10efe5362fab27de29;p=u-boot

diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 71a691b5db..af047e2a07 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
+#include <asm/processor.h>
 
 /* Two MT48LC8M32B2 for 32 MB */
 /* #include "mt48lc8m32b2-6-7.h" */
@@ -43,6 +44,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[];	/* FLASH chips info */
 
+extern int do_auto_update(void);
 ulong flash_get_size (ulong base, int banknum);
 
 #ifndef CFG_RAMBOOT
@@ -90,14 +92,15 @@ static void sdram_start (int hi_addr)
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
- *            is something else than 0x00000000.
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
  */
 
 long int initdram (int board_type)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
+	uint svr, pvr;
 #ifndef CFG_RAMBOOT
 	ulong test1, test2;
 
@@ -192,6 +195,22 @@ long int initdram (int board_type)
 
 #endif /* CFG_RAMBOOT */
 
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
 	return dramsize + dramsize2;
 }
 
@@ -271,6 +290,9 @@ int misc_init_r (void)
 		flash_info[0].sector_count = snum;
 	}
 
+#ifdef CONFIG_AUTO_UPDATE
+	do_auto_update();
+#endif
 	return (0);
 }