X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=board%2Fr2dplus%2Fr2dplus.c;h=8fb8ff667a328a026895507fa708fd6162c7616f;hb=c4b81f3238d77a4df343bd70ddfb7ebd29ca1dda;hp=2ee3ea2f3fcb7d5085fdd3e1d4896bf973e2bd5b;hpb=f5e2466f7baa887a7df0c536333eea8231333497;p=u-boot

diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c
index 2ee3ea2f3f..8fb8ff667a 100644
--- a/board/r2dplus/r2dplus.c
+++ b/board/r2dplus/r2dplus.c
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <ide.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
 int checkboard(void)
@@ -37,7 +38,7 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,25 +53,26 @@ int board_late_init(void)
 	return 0;
 }
 
-#define FPGA_BASE          0xA4000000
-#define FPGA_CFCTL         (FPGA_BASE + 0x04)
-#define FPGA_CFPOW         (FPGA_BASE + 0x06)
-#define FPGA_CFCDINTCLR    (FPGA_BASE + 0x2A)
+#define FPGA_BASE		0xA4000000
+#define FPGA_CFCTL		(FPGA_BASE + 0x04)
+#define CFCTL_EN		(0x432)
+#define FPGA_CFPOW		(FPGA_BASE + 0x06)
+#define CFPOW_ON		(0x02)
+#define FPGA_CFCDINTCLR	(FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN	(0x01)
 
-void ide_set_reset (int idereset)
+void ide_set_reset(int idereset)
 {
 	/* if reset = 1 IDE reset will be asserted */
-	if (idereset){
-		(*(vu_short *)FPGA_CFCTL) = 0x432;
-		(*(vu_short *)FPGA_CFPOW) |= 0x02;
-		(*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+	if (idereset) {
+		outw(CFCTL_EN, FPGA_CFCTL);	/* CF enable */
+		outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+		outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
 	}
 }
 
-#if defined(CONFIG_PCI)
 static struct pci_controller hose;
 void pci_init_board(void)
 {
-	pci_sh7751_init( &hose );
+	pci_sh7751_init(&hose);
 }
-#endif /* CONFIG_PCI */