X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=board%2Fsbc8349%2Fsbc8349.c;h=42f4c1ef06774506a204641e6869c689dbcb4173;hb=721d0b0026971924605701a0e409ded91e093caa;hp=5446c205e10656fbeac83a5efd0e2a0e4d873fb0;hpb=6a40ef62c4300e9f606deef0a4618cbc4b514a51;p=u-boot diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 5446c205e1..42f4c1ef06 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -30,11 +30,8 @@ #include #include #include -#include -#include -#if defined(CONFIG_SPD_EEPROM) #include -#endif +#include #if defined(CONFIG_OF_LIBFDT) #include #endif @@ -42,7 +39,7 @@ int fixed_sdram(void); void sdram_init(void); -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) void ddr_enable_ecc(unsigned int dram_size); #endif @@ -55,16 +52,16 @@ int board_early_init_f (void) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else @@ -91,35 +88,34 @@ long int initdram (int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; /* DDR size in bytes */ + u32 ddr_size_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) +#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CFG_DDR_CONFIG; + +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[2].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; im->ddr.cs_config[1] = 0; im->ddr.cs_config[3] = 0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; im->ddr.sdram_cfg = SDRAM_CFG_SREN @@ -131,16 +127,16 @@ int fixed_sdram(void) /* for 32-bit mode burst length is 8 */ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); #endif - im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; udelay(200); /* enable DDR controller */ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; return msize; } -#endif/*!CFG_SPD_EEPROM*/ +#endif/*!CONFIG_SYS_SPD_EEPROM*/ int checkboard (void) @@ -152,44 +148,44 @@ int checkboard (void) /* * if board is fitted with SDRAM */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#if defined(CONFIG_SYS_BR2_PRELIM) \ + && defined(CONFIG_SYS_OR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWAR2_PRELIM) /* * Initialize SDRAM memory on the Local Bus. */ void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile lbus83xx_t *lbc= &immap->lbus; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ - lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -217,12 +213,12 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ asm("sync"); *sdram_addr = 0xff; udelay(100);