X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=cpu%2Fmpc5xxx%2Fstart.S;h=3936b5551f3c11d33437c755083dfccd4a6fc82a;hb=ec2e5a2ccea77102ba7357d31d5670b4467967d3;hp=a001e1ce404d77a278756aa9b3a5dd7f312f459f;hpb=d4ca31c40e8888b36635967522ec7ea03fd7e70b;p=u-boot

diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index a001e1ce40..3936b5551f 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -29,7 +29,7 @@
 #include <mpc5xxx.h>
 #include <version.h>
 
-#define CONFIG_MPC5XXX 1	/* needed for Linux kernel header files */
+#define CONFIG_MPC5xxx 1	/* needed for Linux kernel header files */
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
 #include <ppc_asm.tmpl>
@@ -103,45 +103,50 @@ boot_cold:
 boot_warm:
 	mfmsr	r5			/* save msr contents		*/
 
+	/* Move CSBoot and adjust instruction pointer                   */
+	/*--------------------------------------------------------------*/
+
 #if defined(CFG_LOWBOOT)
+# if defined(CFG_RAMBOOT)
+#  error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
+# endif /* CFG_RAMBOOT */
+# if defined(CONFIG_MGT5100)
+#  error CFG_LOWBOOT is incompatible with MGT5100
+# endif /* CONFIG_MGT5100 */
 	lis	r4, CFG_DEFAULT_MBAR@h
-	lis	r3,     0x0000FF00@h
-	ori	r3, r3, 0x0000FF00@l
-	stw	r3, 0x4(r4)
-	lis	r3,     0x0000FFFF@h
-	ori	r3, r3, 0x0000FFFF@l
-	stw	r3, 0x8(r4)
-	lis	r3,     0x00047800@h
-	ori	r3, r3, 0x00047800@l
-	stw	r3, 0x300(r4)
+	lis	r3,	START_REG(CFG_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CFG_BOOTCS_START)@l
+	stw	r3, 0x4(r4)		/* CS0 start */
+	lis	r3,	STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+	stw	r3, 0x8(r4)		/* CS0 stop */
 	lis	r3,     0x02010000@h
 	ori	r3, r3, 0x02010000@l
-	stw	r3, 0x54(r4)
+	stw	r3, 0x54(r4)		/* CS0 and Boot enable */
 
-	lis     r3,	lowboot_reentry@h
-	ori     r3, r3, lowboot_reentry@l
+	lis     r3,	lowboot_reentry@h	/* jump from bootlow address space (0x0000xxxx) */
+	ori     r3, r3, lowboot_reentry@l	/* to the address space the linker used */
 	mtlr	r3
-	blr				/* jump to flash based address */
+	blr
 
 lowboot_reentry:
-	lis	r3,     0x0000FF00@h
-	ori	r3, r3, 0x0000FF00@l
-	stw	r3, 0x4c(r4)
-	lis	r3,     0x0000FFFF@h
-	ori	r3, r3, 0x0000FFFF@l
-	stw	r3, 0x50(r4)
-	lis	r3,     0x00047800@h
-	ori	r3, r3, 0x00047800@l
-	stw	r3, 0x300(r4)
+	lis	r3,	START_REG(CFG_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CFG_BOOTCS_START)@l
+	stw	r3, 0x4c(r4)		/* Boot start */
+	lis	r3,	STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+	stw	r3, 0x50(r4)		/* Boot stop */
 	lis	r3,     0x02000001@h
 	ori	r3, r3, 0x02000001@l
-	stw	r3, 0x54(r4)
+	stw	r3, 0x54(r4)		/* Boot enable, CS0 disable */
 #endif	/* CFG_LOWBOOT */
 
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
 	lis	r3, CFG_MBAR@h
 	ori	r3, r3, CFG_MBAR@l
 #if defined(CONFIG_MPC5200)
+	/* MBAR is mirrored into the MBAR SPR */
+	mtspr	MBAR,r3
 	rlwinm	r3, r3, 16, 16, 31
 #endif
 #if defined(CONFIG_MGT5100)
@@ -547,6 +552,11 @@ dcache_status:
 	rlwinm	r3, r3, HID0_DCE_BITPOS + 1, 31, 31
 	blr
 
+	.globl get_svr
+get_svr:
+	mfspr	r3, SVR
+	blr
+
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR