X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=cpu%2Fmpc8260%2Fcpu.c;h=aedbf297ab7833810c4c20b573fcf7841c923c00;hb=abc76eb6a6936a99811eda256222b3927427f8e2;hp=b8ba48cd0493c547911863e910be9360d5b8f3fd;hpb=4532cb696eb717419022dbaa8d408e7df7df7b68;p=u-boot diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index b8ba48cd04..aedbf297ab 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2003 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -22,7 +22,7 @@ */ /* - * CPU specific code for the MPC8255 / MPC8260 CPUs + * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x * * written or collected and sometimes rewritten by * Magnus Damm @@ -35,20 +35,34 @@ * * added 8260 masks by * Marius Groeger + * + * added HiP7 (824x/827x/8280) processors support by + * Yuli Barcohen */ #include #include #include #include +#include #include #include +#if defined(CONFIG_OF_LIBFDT) +#include +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_GET_CPU_STR_F) +extern int get_cpu_str_f (char *buf); +#endif + int checkcpu (void) { - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong clock = gd->cpu_clk; uint pvr = get_pvr (); uint immr, rev, m, k; @@ -56,15 +70,34 @@ int checkcpu (void) puts ("CPU: "); - if (((pvr >> 16) & 0xff) != 0x81) + switch (pvr) { + case PVR_8260: + case PVR_8260_HIP3: + k = 3; + break; + case PVR_8260_HIP4: + k = 4; + break; + case PVR_8260_HIP7R1: + case PVR_8260_HIP7RA: + case PVR_8260_HIP7: + k = 7; + break; + default: return -1; /* whoops! not an MPC8260 */ + } rev = pvr & 0xff; immr = immap->im_memctl.memc_immr; - if ((immr & IMMR_ISB_MSK) != CFG_IMMR) + if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR) return -1; /* whoops! someone moved the IMMR */ - printf (CPU_ID_STR " (Rev %02x, Mask ", rev); +#if defined(CONFIG_GET_CPU_STR_F) + get_cpu_str_f (buf); + printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev); +#else + printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev); +#endif /* * the bottom 16 bits of the immr are the Part Number and Mask Number @@ -78,31 +111,55 @@ int checkcpu (void) switch (m) { case 0x0000: - printf ("0.2 2J24M"); + puts ("0.2 2J24M"); break; case 0x0010: - printf ("A.0 K22A"); + puts ("A.0 K22A"); break; case 0x0011: - printf ("A.1 1K22A-XC"); + puts ("A.1 1K22A-XC"); break; case 0x0001: - printf ("B.1 1K23A"); + puts ("B.1 1K23A"); break; case 0x0021: - printf ("B.2 2K23A-XC"); + puts ("B.2 2K23A-XC"); break; case 0x0023: - printf ("B.3 3K23A"); + puts ("B.3 3K23A"); break; case 0x0024: - printf ("C.2 6K23A"); + puts ("C.2 6K23A"); break; case 0x0060: - printf ("A.0(A) 2K25A"); + puts ("A.0(A) 2K25A"); break; case 0x0062: - printf ("B.1 4K25A"); + puts ("B.1 4K25A"); + break; + case 0x0064: + puts ("C.0 5K25A"); + break; + case 0x0A00: + puts ("0.0 0K49M"); + break; + case 0x0A01: + puts ("0.1 1K49M"); + break; + case 0x0A10: + puts ("1.0 1K49M"); + break; + case 0x0C00: + puts ("0.0 0K50M"); + break; + case 0x0C10: + puts ("1.0 1K50M"); + break; + case 0x0D00: + puts ("0.0 0K50M"); + break; + case 0x0D10: + puts ("1.0 1K50M"); break; default: printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); @@ -122,7 +179,7 @@ int checkcpu (void) void upmconfig (uint upm, uint * table, uint size) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ uint i; @@ -179,12 +236,13 @@ void upmconfig (uint upm, uint * table, uint size) /* ------------------------------------------------------------------------- */ +#if !defined(CONFIG_HAVE_OWN_RESET) int -do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { ulong msr, addr; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ @@ -198,20 +256,21 @@ do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif ((void (*)(void)) addr) (); return 1; } +#endif /* CONFIG_HAVE_OWN_RESET */ /* ------------------------------------------------------------------------- */ @@ -221,8 +280,6 @@ do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { - DECLARE_GLOBAL_DATA_PTR; - ulong tbclk; tbclk = (gd->bus_clk + 3L) / 4L; @@ -237,10 +294,45 @@ void watchdog_reset (void) { int re_enable = disable_interrupts (); - reset_8260_watchdog ((immap_t *) CFG_IMMR); + reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR); if (re_enable) enable_interrupts (); } #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ +#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) +void ft_cpu_setup (void *blob, bd_t *bd) +{ +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + fdt_fixup_ethernet(blob); +#endif + + do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", + "clock-frequency", bd->bi_brgfreq, 1); + + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", OF_TBCLK, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} +#endif /* CONFIG_OF_LIBFDT */ + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_ETHER_ON_FCC) + fec_initialize(bis); +#endif +#if defined(CONFIG_ETHER_ON_SCC) + mpc82xx_scc_enet_initialize(bis); +#endif + return 0; +}