X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fvsc7385.c;h=a5110e516dbeb47d52382ec6b91cdad91f4b71dd;hb=c35cf8dc9fd90ff108abe08527df042bcd29a02f;hp=4095bce5bfcb9009a93660cbfe7fb0075799affa;hpb=4b7a6dd89633d60dc4b58476d5ce48247f82a3ca;p=u-boot

diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
index 4095bce5bf..a5110e516d 100644
--- a/drivers/net/vsc7385.c
+++ b/drivers/net/vsc7385.c
@@ -13,12 +13,10 @@
  */
 
 #include <config.h>
-
-#ifdef CONFIG_VSC7385_ENET
-
 #include <common.h>
 #include <asm/io.h>
 #include <asm/errno.h>
+#include "vsc7385.h"
 
 /*
  * Upload a Vitesse VSC7385 firmware image to the hardware
@@ -38,13 +36,13 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size)
 	u8 *fw = firmware;
 	unsigned int i;
 
-	u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
-	u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
-	u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
-	u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
-	u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
+	u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
+	u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
+	u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
+	u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
+	u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
 #ifdef DEBUG
-	u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
+	u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
 #endif
 
 	out_be32(gloreset, 3);
@@ -97,5 +95,3 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size)
 
 	return 0;
 }
-
-#endif