X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fzynq_gem.c;h=519699d8ff020fb1b64ed12d763658b46502acd2;hb=b10335009667fee493fbce59bbeb0504d0ca9ff0;hp=a569c77aeb602161e74966d610ee7ea5300efc63;hpb=687d73126361b45f77f977301d141771babd02c0;p=u-boot diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a569c77aeb..519699d8ff 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -10,22 +10,23 @@ */ #include +#include #include #include #include +#include #include #include #include #include +#include #include #include #include #include #include -#if !defined(CONFIG_PHYLIB) -# error XILINX_GEM_ETHERNET requires PHYLIB -#endif +DECLARE_GLOBAL_DATA_PTR; /* Bit/mask specification */ #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ @@ -56,7 +57,13 @@ #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ +#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ +#define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ +#ifdef CONFIG_ARM64 +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ +#else #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ +#endif #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ @@ -86,6 +93,8 @@ #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ +#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -132,7 +141,9 @@ struct zynq_gem_regs { u32 reserved6[18]; #define STAT_SIZE 44 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ - u32 reserved7[164]; + u32 reserved9[20]; + u32 pcscntrl; + u32 reserved7[143]; u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ u32 reserved8[15]; u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ @@ -168,6 +179,7 @@ struct zynq_gem_priv { struct zynq_gem_regs *iobase; phy_interface_t interface; struct phy_device *phydev; + int phy_of_handle; struct mii_dev *bus; }; @@ -241,7 +253,7 @@ static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); } -static int phy_detection(struct eth_device *dev) +static int phy_detection(struct udevice *dev) { int i; u16 phyreg; @@ -280,20 +292,22 @@ static int phy_detection(struct eth_device *dev) return -1; } -static int zynq_gem_setup_mac(struct eth_device *dev) +static int zynq_gem_setup_mac(struct udevice *dev) { u32 i, macaddrlow, macaddrhigh; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; /* Set the MAC bits [31:0] in BOT */ - macaddrlow = dev->enetaddr[0]; - macaddrlow |= dev->enetaddr[1] << 8; - macaddrlow |= dev->enetaddr[2] << 16; - macaddrlow |= dev->enetaddr[3] << 24; + macaddrlow = pdata->enetaddr[0]; + macaddrlow |= pdata->enetaddr[1] << 8; + macaddrlow |= pdata->enetaddr[2] << 16; + macaddrlow |= pdata->enetaddr[3] << 24; /* Set MAC bits [47:32] in TOP */ - macaddrhigh = dev->enetaddr[4]; - macaddrhigh |= dev->enetaddr[5] << 8; + macaddrhigh = pdata->enetaddr[4]; + macaddrhigh |= pdata->enetaddr[5] << 8; for (i = 0; i < 4; i++) { writel(0, ®s->laddr[i][LADDR_LOW]); @@ -308,11 +322,11 @@ static int zynq_gem_setup_mac(struct eth_device *dev) return 0; } -static int zynq_phy_init(struct eth_device *dev) +static int zynq_phy_init(struct udevice *dev) { int ret; - struct zynq_gem_priv *priv = dev->priv; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -323,10 +337,12 @@ static int zynq_phy_init(struct eth_device *dev) /* Enable only MDIO bus */ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); - ret = phy_detection(dev); - if (ret) { - printf("GEM PHY init failed\n"); - return ret; + if (priv->interface != PHY_INTERFACE_MODE_SGMII) { + ret = phy_detection(dev); + if (ret) { + printf("GEM PHY init failed\n"); + return ret; + } } priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, @@ -337,17 +353,20 @@ static int zynq_phy_init(struct eth_device *dev) priv->phydev->supported = supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; priv->phydev->advertising = priv->phydev->supported; - phy_config(priv->phydev); - return 0; + if (priv->phy_of_handle > 0) + priv->phydev->dev->of_offset = priv->phy_of_handle; + + return phy_config(priv->phydev); } -static int zynq_gem_init(struct eth_device *dev, bd_t *bis) +static int zynq_gem_init(struct udevice *dev) { - u32 i; + u32 i, nwconfig; + int ret; unsigned long clk_rate = 0; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - struct zynq_gem_priv *priv = dev->priv; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; @@ -412,21 +431,34 @@ static int zynq_gem_init(struct eth_device *dev, bd_t *bis) priv->init++; } - phy_startup(priv->phydev); + ret = phy_startup(priv->phydev); + if (ret) + return ret; if (!priv->phydev->link) { printf("%s: No link.\n", priv->phydev->dev->name); return -1; } + nwconfig = ZYNQ_GEM_NWCFG_INIT; + + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { + nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | + ZYNQ_GEM_NWCFG_PCS_SEL; +#ifdef CONFIG_ARM64 + writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, + ®s->pcscntrl); +#endif + } + switch (priv->phydev->speed) { case SPEED_1000: - writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: - writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, ®s->nwcfg); clk_rate = ZYNQ_GEM_FREQUENCY_100; break; @@ -437,7 +469,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t *bis) /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) - zynq_slcr_gem_clk_setup(dev->iobase != + zynq_slcr_gem_clk_setup((ulong)priv->iobase != ZYNQ_GEM_BASEADDR0, clk_rate); setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | @@ -446,38 +478,11 @@ static int zynq_gem_init(struct eth_device *dev, bd_t *bis) return 0; } -static int wait_for_bit(const char *func, u32 *reg, const u32 mask, - bool set, unsigned int timeout) -{ - u32 val; - unsigned long start = get_timer(0); - - while (1) { - val = readl(reg); - - if (!set) - val = ~val; - - if ((val & mask) == mask) - return 0; - - if (get_timer(start) > timeout) - break; - - udelay(1); - } - - debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", - func, reg, mask, set); - - return -ETIMEDOUT; -} - -static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) +static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { u32 addr, size; - struct zynq_gem_priv *priv = dev->priv; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; struct emac_bd *current_bd = &priv->tx_bd[1]; /* Setup Tx BD */ @@ -514,101 +519,116 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) printf("TX buffers exhausted in mid frame\n"); return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, - true, 20000); + true, 20000, true); } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ -static int zynq_gem_recv(struct eth_device *dev) +static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) { int frame_len; - struct zynq_gem_priv *priv = dev->priv; + u32 addr; + struct zynq_gem_priv *priv = dev_get_priv(dev); struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; - struct emac_bd *first_bd; if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) - return 0; + return -1; if (!(current_bd->status & (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { printf("GEM: SOF or EOF not set for last buffer received!\n"); - return 0; + return -1; } frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; - if (frame_len) { - u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; - addr &= ~(ARCH_DMA_MINALIGN - 1); + if (!frame_len) { + printf("%s: Zero size packet?\n", __func__); + return -1; + } - net_process_received_packet((u8 *)(ulong)addr, frame_len); + addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; + addr &= ~(ARCH_DMA_MINALIGN - 1); + *packetp = (uchar *)(uintptr_t)addr; - if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) - priv->rx_first_buf = priv->rxbd_current; - else { - current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; - current_bd->status = 0xF0000000; /* FIXME */ - } + return frame_len; +} - if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { - first_bd = &priv->rx_bd[priv->rx_first_buf]; - first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; - first_bd->status = 0xF0000000; - } +static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; + struct emac_bd *first_bd; - if ((++priv->rxbd_current) >= RX_BUF) - priv->rxbd_current = 0; + if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { + priv->rx_first_buf = priv->rxbd_current; + } else { + current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + current_bd->status = 0xF0000000; /* FIXME */ } - return frame_len; + if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { + first_bd = &priv->rx_bd[priv->rx_first_buf]; + first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + first_bd->status = 0xF0000000; + } + + if ((++priv->rxbd_current) >= RX_BUF) + priv->rxbd_current = 0; + + return 0; } -static void zynq_gem_halt(struct eth_device *dev) +static void zynq_gem_halt(struct udevice *dev) { - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } -static int zynq_gem_miiphyread(const char *devname, uchar addr, - uchar reg, ushort *val) +__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) { - struct eth_device *dev = eth_get_dev(); - struct zynq_gem_priv *priv = dev->priv; - int ret; - - ret = phyread(priv, addr, reg, val); - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); - return ret; + return -ENOSYS; } -static int zynq_gem_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) +static int zynq_gem_read_rom_mac(struct udevice *dev) { - struct eth_device *dev = eth_get_dev(); - struct zynq_gem_priv *priv = dev->priv; + int retval; + struct eth_pdata *pdata = dev_get_platdata(dev); + + retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); + if (retval == -ENOSYS) + retval = 0; - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); - return phywrite(priv, addr, reg, val); + return retval; } -int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, - int phy_addr, u32 emio) +static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) { + struct zynq_gem_priv *priv = bus->priv; int ret; - struct eth_device *dev; - struct zynq_gem_priv *priv; - void *bd_space; + u16 val; - dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -1; + ret = phyread(priv, addr, reg, &val); + debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); + return val; +} - dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); - if (dev->priv == NULL) { - free(dev); - return -1; - } - priv = dev->priv; +static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) +{ + struct zynq_gem_priv *priv = bus->priv; + + debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); + return phywrite(priv, addr, reg, value); +} + +static int zynq_gem_probe(struct udevice *dev) +{ + void *bd_space; + struct zynq_gem_priv *priv = dev_get_priv(dev); + int ret; /* Align rxbuffers to ARCH_DMA_MINALIGN */ priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); @@ -623,34 +643,90 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); - priv->phyaddr = phy_addr; - priv->emio = emio; + priv->bus = mdio_alloc(); + priv->bus->read = zynq_gem_miiphy_read; + priv->bus->write = zynq_gem_miiphy_write; + priv->bus->priv = priv; + strcpy(priv->bus->name, "gem"); -#ifndef CONFIG_ZYNQ_GEM_INTERFACE - priv->interface = PHY_INTERFACE_MODE_MII; -#else - priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; -#endif + ret = mdio_register(priv->bus); + if (ret) + return ret; - sprintf(dev->name, "Gem.%lx", base_addr); + return zynq_phy_init(dev); +} - dev->iobase = base_addr; - priv->iobase = (struct zynq_gem_regs *)base_addr; +static int zynq_gem_remove(struct udevice *dev) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); - dev->init = zynq_gem_init; - dev->halt = zynq_gem_halt; - dev->send = zynq_gem_send; - dev->recv = zynq_gem_recv; - dev->write_hwaddr = zynq_gem_setup_mac; + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); - eth_register(dev); + return 0; +} - miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); - priv->bus = miiphy_get_dev_by_name(dev->name); +static const struct eth_ops zynq_gem_ops = { + .start = zynq_gem_init, + .send = zynq_gem_send, + .recv = zynq_gem_recv, + .free_pkt = zynq_gem_free_pkt, + .stop = zynq_gem_halt, + .write_hwaddr = zynq_gem_setup_mac, + .read_rom_hwaddr = zynq_gem_read_rom_mac, +}; - ret = zynq_phy_init(dev); - if (ret) - return ret; +static int zynq_gem_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->iobase = (struct zynq_gem_regs *)pdata->iobase; + /* Hardcode for now */ + priv->emio = 0; + priv->phyaddr = -1; + + priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, + dev->of_offset, "phy-handle"); + if (priv->phy_of_handle > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, + priv->phy_of_handle, "reg", -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + priv->interface = pdata->phy_interface; + + priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); + + printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, + priv->phyaddr, phy_string_for_interface(priv->interface)); - return 1; + return 0; } + +static const struct udevice_id zynq_gem_ids[] = { + { .compatible = "cdns,zynqmp-gem" }, + { .compatible = "cdns,zynq-gem" }, + { .compatible = "cdns,gem" }, + { } +}; + +U_BOOT_DRIVER(zynq_gem) = { + .name = "zynq_gem", + .id = UCLASS_ETH, + .of_match = zynq_gem_ids, + .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, + .probe = zynq_gem_probe, + .remove = zynq_gem_remove, + .ops = &zynq_gem_ops, + .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +};