X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fpci%2Fpcie_layerscape_fixup.c;h=1a17bd98aa4ca3fe3081a99f20c61e351b718034;hb=680a52c35088dc30a4ca18870ec89ff3e1ac0e52;hp=d504bbda378b636dc93ab38732b2060ff7cfe086;hpb=f532703665ae5e5957211bbc4e7296a8313cc403;p=u-boot

diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index d504bbda37..1a17bd98aa 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,8 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -11,8 +11,11 @@
 #include <asm/io.h>
 #include <errno.h>
 #ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
+#include <linux/libfdt.h>
 #include <fdt_support.h>
+#ifdef CONFIG_ARM
+#include <asm/arch/clock.h>
+#endif
 #include "pcie_layerscape.h"
 
 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
@@ -82,7 +85,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+		    svr == SVR_LS2081A || svr == SVR_LS2041A)
 			compat = "fsl,ls2088a-pcie";
 		else
 			compat = CONFIG_FSL_PCIE_COMPAT;
@@ -125,19 +129,28 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
 	u32 iommu_map[4];
 	int nodeoffset;
 	int lenp;
+	uint svr;
+	char *compat = NULL;
 
 	/* find pci controller node */
 	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 						   pcie->dbi_res.start);
 	if (nodeoffset < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
-		nodeoffset = fdt_node_offset_by_compat_reg(blob,
-				CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+		    svr == SVR_LS2081A || svr == SVR_LS2041A)
+			compat = "fsl,ls2088a-pcie";
+		else
+			compat = CONFIG_FSL_PCIE_COMPAT;
+
+		if (compat)
+			nodeoffset = fdt_node_offset_by_compat_reg(blob,
+						compat, pcie->dbi_res.start);
+#endif
 		if (nodeoffset < 0)
 			return;
-#else
-		return;
-#endif
 	}
 
 	/* get phandle to iommu controller */
@@ -217,7 +230,8 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+		    svr == SVR_LS2081A || svr == SVR_LS2041A)
 			compat = "fsl,ls2088a-pcie";
 		else
 			compat = CONFIG_FSL_PCIE_COMPAT;