X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fpower%2Ftwl4030.c;h=8866bf1b19edb4ae4731eabacf434c501435a3d2;hb=009902a871dcb1ad60e746280372f47d90f65353;hp=6610f787d0c7795a656619b28718944b84202fd1;hpb=cac423a730d3506154744485af1bbc1cd3a1e6a8;p=u-boot

diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index 6610f787d0..8866bf1b19 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -2,20 +2,7 @@
  * Copyright (c) 2009 Wind River Systems, Inc.
  * Tom Rix <Tom.Rix at windriver.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  *
  * twl4030_power_reset_init is derived from code on omapzoom,
  * git://git.omapzoom.com/repo/u-boot.git
@@ -34,7 +21,6 @@
  * Derived from Beagle Board and 3430 SDP code by
  *	Richard Woodruff <r-woodruff2 at ti.com>
  *	Syed Mohammed Khasim <khasim at ti.com>
- *
  */
 
 #include <twl4030.h>
@@ -59,6 +45,66 @@ void twl4030_power_reset_init(void)
 	}
 }
 
+/*
+ * Power off
+ */
+void twl4030_power_off(void)
+{
+	u8 data;
+
+	/* PM master unlock (CFG and TST keys) */
+
+	data = 0xCE;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, data);
+	data = 0xEC;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, data);
+
+	/* VBAT start disable */
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_P1_TRANSITION, &data);
+	data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_P1_TRANSITION, data);
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_P2_TRANSITION, &data);
+	data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_P2_TRANSITION, data);
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_P3_TRANSITION, &data);
+	data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_P3_TRANSITION, data);
+
+	/* High jitter for PWRANA2 */
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_PWRANA2, &data);
+	data &= ~(TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV |
+		  TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_PWRANA2, data);
+
+	/* PM master lock */
+
+	data = 0xFF;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, data);
+
+	/* Power off */
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_P1_SW_EVENTS, &data);
+	data |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_P1_SW_EVENTS, data);
+}
+
 /*
  * Set Device Group and Voltage
  */
@@ -105,11 +151,23 @@ void twl4030_power_init(void)
 				TWL4030_PM_RECEIVER_DEV_GRP_P1);
 }
 
-void twl4030_power_mmc_init(void)
+void twl4030_power_mmc_init(int dev_index)
 {
-	/* Set VMMC1 to 3.15 Volts */
-	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
-				TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
-				TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
-				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	if (dev_index == 0) {
+		/* Set VMMC1 to 3.15 Volts */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
+					TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
+					TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+		mdelay(100);	/* ramp-up delay from Linux code */
+	} else if (dev_index == 1) {
+		/* Set VMMC2 to 3.15 Volts */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+					TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+					TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+		mdelay(100);	/* ramp-up delay from Linux code */
+	}
 }